Denso Corporation

Nippondenso Co., Ltd.

Anden Co., Ltd.

Hiroyuki Ban

Junji Hayakawa

Mitsuhiro Saitou

Junichi Nagata

Tomohisa Yamamoto

Satoshi Shiraki

Hiroshi Imai

Makio Iida

Hirokazu Itakura

Takahisa Koyasu

Akira Yamada

Fukuo Ishikawa

Kiyoshi Yamamoto

Takeshi Miki

Hiroshi Fujimoto

Hiroshi Maeda

Shoji Miura

Toshio Sakakibara

Akira Sugiura

Yoshiaki Nakayama

Hirofumi Abe

Shoichi Okuda

Shigeki Takahashi

Hajime Ito

Takashi Nagasaka

Shoji Mizuno

Hiroaki Himi

Takeshi Ishikawa

Naohito Mizuno

Takashi Harada

Yoshihiko Isobe

Takayuki Sugisaka

Yasuhiro Kitamura

Mitsuru Aoki

Satoshi Sobue

Tetsuya Katayama

Masami Kataoka

Masakazu Honda

Masahiro Kitagawa

Kengo Oka

Koji Numazaki

Shinichi Hirose

Shinichiro Nakata

Shigenori Mori

Katsumi Nakamura

Nobuyoshi Osamura

Kingo Ota

Kenji Kohno

Tadashi Suzuki

Akitaka Murata

Kouji Numazaki

Katsuhito Takeuchi

Shinichi Maeda

Hiroyuki Ina

Yuji Otani

Satoshi Ichikawa

Takaharu Hutamura

Katsuyuki Miyake

Masahisa Makino

Jyunichi Nagata

Osamu Seya

Hiroyuki Kawabata

Katsuyoshi Oda

Kanemitsu Terada

Tukasa Miyake

Kyoko Nagaoka

A load driving device includes: an output power device for driving a load; a driving IC for controlling the output power device, wherein the driving IC is electrically coupled with the output power device through a wire or a connection member; and a first electrode substrate. The output power device and the driving IC are mounted on the first electrode substrate. In this case, the output power device is controlled with high speed, and a mounting area of the output power device and the driving IC is reduced.

Load driving device

A semiconductor device includes: n transistor elements; n resistive elements; and n capacitive elements, each kind of elements coupled in series between the first and second terminals. The gate of each transistor element has a gate pad, and each transistor element includes transistor pads disposed on both sides. Each resistive element includes resistive pads disposed on both sides. Each capacitive element includes capacitive pads disposed on both sides. The gate pad other than the first stage transistor element, a corresponding resistive pad, and a corresponding capacitive pad are electrically coupled. One transistor pad, one resistive pad, and one capacitive pad in the first stage are electrically coupled. One transistor pad, one resistive pad, and one capacitive pad in the n-th stage are electrically coupled.

Semiconductor device and method for manufacturing the same

A level shift circuit includes a first capacitor circuit including capacitors connected in series between a ground and a predetermined potential, a first trigger circuit coupled to the predetermined potential side of the first capacitor circuit, an input terminal coupled to the ground side of the first capacitor circuit, a second capacitor circuit including capacitors connected in series between the ground and the predetermined potential, a second trigger circuit coupled to the predetermined potential side of the second capacitor circuit, an inverter coupled between the input terminal and the ground potential side of the second capacitor circuit, and a SR latch circuit having a first input coupled to an output of the first trigger circuit and a second input coupled to an output of the second trigger circuit.

Level shift circuit

A current mirror circuit includes transistors having bases coupled together and emitters connected to a voltage line. The current mirror circuit further includes a zener diode having an anode connected to the bases and a cathode connected to the voltage line. When a base potential of the transistors decreases, a reverse current of the zener diode increases. Therefore, the zener diode has a resistance and acts as a resistor to clamp the base potential of the transistors. A layout area of the zener diode is much smaller than that of the resistor having a resistance equal to that of the zener diode. The current mirror circuit achieves reduced chip size by using the zener diode instead of the resistor.

Current mirror circuit for reducing chip size

An input protection circuit comprises a reverse flow preventing diode, a series circuit of a diode and a Zener diode, and a current path forming resistor or diode. The reverse flow preventing diode is connected between an input terminal and an internal circuit. The series circuit is connected between the input terminal and a ground. The current path forming resistor or diode is connected between a first common connection point of the reverse flow preventing diode and the internal circuit and a second common connection point of the series circuit, and sets a potential at the first common connection point to be less than a potential at the input terminal when the surge voltage is applied to the input terminal.

Input protection circuit

A semiconductor device is composed of a heat sink, an IC chip mounted and fixed on a specific face of the heat sink, a lead frame electrically connected to the IC chip and a sealing mold resin package. One or more of the faces of the heat sink has a specific surface area.

Semiconductor device

In a power supply apparatus, a switching circuit selectively applies one of an input voltage of a power converting circuit and an output voltage of the power converting circuit to a voltage reducing power supply circuit. When the input voltage is applied to the power converting circuit, the switching circuit selects this input voltage, so that the output voltage of the voltage reducing power supply circuit can quickly rise. Thereafter, when the output voltage of the power converting circuit exceeds this output voltage, the switching circuit selects the output voltage of the power converting circuit. As a result, a difference between the input voltage and the output voltage of the voltage reducing power supply circuit is decreased. Thus, a power loss is lowered and noise produced in the power converting circuit is suppressed.

Electric power supply apparatus having input switching circuit

In a power supply circuit, a main transistor, which transmits power from an input terminal to an output terminal, is controlled so that a detected voltage from an input voltage is consistent with a reference voltage indicating a target voltage. An output current is detected and a limited value of the output current is set so that the limited value increases gradually when the output voltage rises up to the target voltage. The main transistor is controlled so that the output current keeps a value less than or equal to the limited value. This configuration is able to suppress an overshoot of the output voltage, thanks to a gradually raised control of the limited value. Additionally, to avoid the influence of a ringing component of the input voltage, a delay control circuit to give a delay to the start of rise of the output voltage can be provided.

Power supply circuit with control of rise characteristics of output voltage

A semiconductor device includes a substrate, a plurality of bump electrodes disposed on the substrate, and a support area for supporting the substrate in case of carrying the substrate. The support area is disposed on a surface of the substrate, on which the bump electrode is disposed, and is disposed at a predetermined position, which is dotted on the surface of the substrate. In this device, the support area is sufficiently small, and the number of the bump electrodes can increase. Moreover, degree of freedom in a configuration of the support area increases.

Semiconductor device having bump electrode and support area

In a voltage booster, a voltage detection circuit detects a battery voltage as an input voltage. If the input voltage is lower than a threshold level, an oscillation circuit outputs a gate signal having a relatively high frequency to increase the driving performance of a driving circuit. If the input voltage is higher than the threshold level, the frequency of the gate signal is lowered so as to prevent the driving performance of the driving circuit from rising to an excessively high value. As a result, a predetermined boosted voltage can be obtained regardless of variations in input voltage without using a filter for eliminating noise.

Voltage booster having noise reducing structure

In an operational amplifier, a differential amplifying circuit is configured to amplify an input voltage inputted from the input terminal. An outputting transistor is connected to the output terminal. A driving transistor is connected to the differential amplifying circuit and the outputting transistor. The driving transistor turns on according to a control signal supplied from the differential amplifying circuit to the driving circuit. The driving transistor is also configured to drive the outputting transistor according to the control signal. A control signal reducing circuit, when a voltage is applied on the driving transistor through the outputting transistor, is configured to reduce the control signal within a range that the driving transistor is kept to on state. The voltage applied on the driving transistor exceeds a predetermined threshold voltage.

Operational amplifier

A semiconductor device is provided having a power transistor structure. The power transistor structure includes a plurality of first wells disposed independently at a surface portion of a semiconductor layer; a deep region having a portion disposed in the semiconductor layer between the first wells; a drain electrode connected to respective drain regions in the first wells; a source electrode connected to respective source regions and channel well regions in the first wells, such that either the drain electrode or the source electrode is connected to an inductive load; and a connecting member for supplying the deep region with a source potential, where the connecting member is configurable to connect to the drain electrode when the drain electrode is connected to the inductive load and to connect to the source electrode when the source electrode is connected to said inductive load.

Power MOS transistor for absorbing surge current

An NPN bipolar transistor and a PNP bipolar transistor are formed in a semiconductor substrate. The NPN bipolar transistor has a p type emitter region, a p type collector region and an n type base region and is formed in an NPN forming region. The PNP bipolar transistor has an n type emitter region, an n type collector region and a p type base region and is formed in a PNP forming region. Only one conductive type burying region is formed in at least one of the NPN forming region and the PNP forming region. A current that flows from the p type emitter region to the n type base region flows in the n type base region in a direction perpendicular to the substrate.

Semiconductor device having bipolar transistors

A semiconductor device includes an output power device, which generates an electrical noise, and an on-chip circuit, to which the noise is transmitted. The output power device is surrounded by two isolating regions. The area between the two isolating regions is electrically connected to a field ground area by a first wiring line. The field ground area is electrically connected to a point of contact, which has ground potential. The area between the outer isolating region of the two isolating regions and another isolating region around the on-chip circuit is also electrically connected to the field ground area by a second wiring line. The first and second wiring lines are separated from each other. The electrical noise is transmitted to the field ground area and released to the point of contact. Therefore, the noise is attenuated and the transmission of the noise to the on-chip circuit is suppressed.

Semiconductor device having isolating region for suppressing electrical noise

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Hazu-gun, Japan

Hiroyuki Ban