Sanyo Electric Co., Ltd.

Semiconductor Components Industries, LLC

Sanyo Semiconductor Co., Ltd.

Hiroyuki Arai

Tetsuya Tokunaga

Takeshi Kimura

Shuji Motegi

Naobumi Nagasawa

Syuji Motegi

Yasuo Osawa

Yoshiyuki Yamagata

Takeshi Hibino

Kensuke Goto

Mamoru Yamaguchi

Teruo Houshi

Ryouichi Ando

In some embodiments, a semiconductor device includes a fuse having a conductive portion configured to be blown when a current exceeding a rated value flows through the conductive portion, a first monitor wiring configured to monitor blowing of the conductive portion of the fuse, and a second monitor wiring configured to monitor blowing of the conductive portion of the fuse. The first monitor wiring and the second monitor wiring are connected to the conductive portion of the fuse so as to be away from a longitudinal center of the conductive portion.

Semiconductor device and method of monitoring blowing of fuse in semiconductor device

A data processing circuit comprising: a first circuit configured to time-division-multiplex a first digital signal synchronous with a clock signal input from an external controller and a second digital signal asynchronous with the clock signal; and a second circuit configured to output a digital signal time-division-multiplexed by the first circuit to the controller.

Data processing circuit and data processing method

A data output circuit includes: a data generating circuit configured to generate output data; and a serial output circuit configured to receive an address corresponding to the data generating circuit, hold a parallel data input during a time period over which the address is being received, and serially output the output data generated by the data generating circuit and the held parallel data in accordance with an output direction signal for directing output of the data.

Data output circuit

Increase in power consumption and increase in power supply noise of a serial data input system are suppressed, while clock skew is more easily prevented. The serial data input system of this invention includes a shift register that takes in and shifts serially transferred display data in synchronization with a clock SCL, a clock counter that counts the number of clock pulses of the clock SCL and outputs each of clock count signals BIT, BITand BITwhen the counted number of the clock pulses of the clock SCL reaches each of count numbersandrespectively, and registers into each of which the data stored in the shift register is transferred and stored collectively and in parallel in response to each of the clock count signals BIT, BIPand BITrespectively.

Serial data input system

An interface circuit outputting a clock signal and data to a data register configured to serially read in the data synchronously with the clock signal, in response to a change of a control signal for outputting the clock signal and the data from one logic level to the other logic level, the interface circuit comprising a clock output circuit configured to: detect a logic level of the clock signal when the control signal changes from the one logic level to the other logic level; output the clock signal on an as-is basis to the data register, when detecting one logic level of the clock signal; and output the clock signal after having changed from the other logic level to the one logic level, to the data register, when detecting the other logic level of the clock signal.

Interface circuit and a clock output method therefor

A driving circuit for a vacuum fluorescent display having a filament, a grid electrode and a segment electrode, the driving circuit comprising a filament driving unit for driving the filament; a grid driving unit for pulse-driving the grid electrode; and a segment driving unit for pulse-driving the segment electrode, wherein the driving circuit comprises a controlling unit for validating or invalidating the output of the filament driving unit at a proper timing.

Driving circuit for vacuum fluorescent display

A driving circuit for a vacuum fluorescent display for pulse-driving a filament of the vacuum fluorescent display with a pulse voltage. The driving circuit comprises a detecting unit for detecting that the level of the pulse voltage is fixed, and outputs a detection signal indicative of the result of the detection. Preferably, the driving circuit comprises a control unit for controlling at least one output of the outputs of the filament driving unit, the grid driving unit and the segment driving unit in order to terminate the driving of at least one of the filament, the grid electrode and the segment electrode, based on the detection signal.

A driving circuit for a vacuum fluorescent display having a filament, a grid electrode and a segment electrode, comprising a grid driving unit for pulse-driving the grid electrode, a segment driving unit for pulse-driving the segment electrode, a first controlling unit for rendering adjustable the duty ratio of the output of the grid driving unit, a second controlling unit for rendering adjustable the duty ratio of the output of the segment driving unit, and a selecting unit for selecting the first controlling unit and/or the second controlling unit.

An interface circuit which outputs a clock signal and data to a data register that serially reads in the data synchronously with the clock signal, in response to a control signal changing from one level to the other level, for outputting the clock signal and the data. The interface circuit comprises a clock output circuit that, responding to the level of the clock signal when the control signal changes from the one level to the other level, outputs clocks of the clock signal that are the same in number as bits of the data to the data register.

A frequency adjustment circuit that maintains a target frequency even when frequency adjustment data of zapping circuit is changed by an external noise is offered. The frequency adjustment circuit includes a reset signal generation circuit, a frequency adjustment data latch circuit that latches and retains the frequency adjustment data ZPand ZPgenerated by a first zapping circuit and a second zapping circuit based on a latch clock ZCLK and a latch clock generation circuit that generates the latch clock ZCLK. The reset signal generation circuit generates a periodic reset signal ZRES that is synchronized with a rise of an enable signal EN generated from an interface circuit. The latch clock generation circuit generates the latch clock ZCLK that is synchronized with a fall of the enable signal EN.

Frequency adjustment circuit

A liquid crystal driving integrated circuit capable of adjusting display contrast and requiring no externally attached components. A resistor formed by four serially connected resistor elements R has one end connected to a reference voltage VLCD applied from an operational amplifier and the other end connected to an external variable resistor through a terminal Consequently, liquid crystal driving voltages VLCD VLCD VLCD VLCD and VLCD can be finely adjusted not only by eleven versions of reference voltage VLCD in accordance with voltages at respective connection points of twelve serially connected resistor elements, but by changing the resistance of the external variable resistor to thereby provide a liquid crystal driving integrated circuit that can be used for a variety of general purposes. Since only one external variable resistor is required and this resistor is inherently variable, there is no need to consider variation in characteristics.

Integrated circuit for driving liquid crystal

A liquid crystal driving integrated circuit capable of adjusting display contrast and requiring no externally attached components. Transmission gates TG -TG are provided at respective connection points of twelve resistor elements connected in series between a power supply and the ground. One of the voltages V -V derived from the transmission gates TG -TG in accordance with control signals CA -CA is applied to an operational amplifier and used as a reference voltage VLCD . The control signals CA -CA are obtained by decoding control data D -D supplied from an external source by a decoder Therefore, the reference voltage VLCD can be set in a plurality of stages simply by changing control data D -D to a user specified value. As the twelve resistor elements connected in series are formed on the same semiconductor substrate, display contrast can be adjusted without requiring any external components attached to a liquid crystal driving integrated circuit

For changing the content of a display RAM (,) or an accessory RAM (,), various data SDI, such as an instruction code, address data, display data, is initially transferred to a shift register (,). Then, the display data in the shift register (,) is latched by a latch circuit (,). A write operation is carried out during a period from the completion of a shift operation by the shift register (,) using various data SDI in connection with the current display to the completion of a shift operation using various data SDI in connection with the next display, i.e., a period with an operation enable signal CE remaining at an L or H level. As a result, time allowance for writing is ensured, which contributes to reduction of software processing load by an external device.

Display driving circuit for displaying character on display panel

A track search circuit includes a command decoder which decodes command data sent by a microcomputer and stored in a command register and outputs signals commanding a track jump and commanding count of a counter which counts a tracking error signal. Time difference between a present A-time and a target A-time is calculated such that an optical pick-up can be moved toward a target position by utilizing the track jump of 4.sup.n. When a counted value of the counter reaches a predetermined value, the A-time is renewed such that the time difference can be reduced by addition or subtraction suitable time data to or from the A-time. If the renewed A-time becomes within 1 minutes with respect to the target A-time in repeating such a track jump in accordance with the renewed A-time, the optical pick-up is stopped to move, and the A-time is read to jump the optical pick-up again to catch the target position.

Circuit and method for searching track on CD

A track search circuit includes a command decoder which decodes command data sent by a microcomputer and stored in a command register and outputs signals commanding a track jump and commanding count of a counter which counts a tracking error signal. Time difference between a present A-time and a target A-time is calculated such that an optical pick-up can be moved toward a target position by utilizing the track jump of 4.sup.n. When a counted value of the counter reaches a predetermined value, the A-time is renewed such that the time difference can be reduced by addition or subtraction suitable time data to or from the A-time. If the renewed A-time becomes within 1 minute with respect to the target A-time in repeating such a track jump in accordance with the renewed A-time, the optical pick-up is stopped to move, and the A-time is read to jump the optical pick-up again to catch the target position.

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Gunma, Japan

Hiroyuki Arai