Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Renesas Electronics Corporation

Other

Mitsubushi Denki Kabushiki Kaisha

Hiroyuki Amishiro

Motoshige Igarashi

Kenji Yamaguchi

Keiichi Higashitani

Toshio Kumamoto

Hirofumi Shinohara

Masao Sugiyama

Akihiko Harada

Kumiko Fujimori

Hideyo Haruhana

Yuko Maruyama

A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

Semiconductor device

Semiconductor device having resistor elements and method for manufacturing the same

Semiconductor device with resistor elements formed on insulating film

To provide a semiconductor device with reduced parasitic capacity in the vicinity of gate electrodes, and a method for manufacturing such a semiconductor device. The semiconductor device comprises a gate electrode formed on a silicon semiconductor substratethrough a gate oxide film, and a pair of impurity diffusion layers formed on the surface region of the silicon semiconductor substrate at both sides of the gate electrode. A silicon nitride film acting as a sidewall spacer is formed so as to cover the sidewall of the gate electrode, and the silicon nitride film is allowed to extend to the surface of the silicon semiconductor substratein the vicinity of the gate electrode in a substantially L-shaped profile.

Semiconductor device and method for manufacturing the same

A semiconductor device including an interconnection structure having superior electrical characteristics and allowing higher speed of operation and lower power consumption even when miniaturized, manufacturing method thereof and a method of designing a semiconductor circuit used in the manufacturing method are provided. In the semiconductor device, a conductive region is formed on a main surface of a semiconductor substrate. A first interconnection layer is electrically connected to the conductive region, has a relatively short line length, and contains a material having relatively high electrical resistance. A first insulator is formed to surround the first interconnection layer and has a relatively low dielectric constant. A second interconnection layer is formed on the main surface of the semiconductor substrate, contains a material having low electrical resistance than the material contained in the first interconnection layer, and has longer line length than the first interconnection layer. A second insulator is formed to surround the second interconnection layer and has a dielectric constant higher than the first insulator.

Semiconductor device including a plurality of interconnection layers, manufacturing method thereof and method of designing semiconductor circuit used in the manufacturing method

Apparatus, method and pattern for evaluating semiconductor device characteristics

Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of salicide structure are provided together, and a method of manufacturing the same. Each gate electrode ( ) of gate structures (GT to GT ) is covered with an upper nitride film ( ) and sidewall nitride film ( ). Therefore, when an interlayer insulating film ( ) being oxide film is selectively removed for forming contact holes (CH and CH ), the upper nitride film ( ) and sidewall nitride film ( ) are not removed, thereby preventing the gate electrode ( ) from being exposed. Particularly, in the gate structures (GT and GT ), even when the contact hole (CH ) is dislocated to either side, no short-circuit is developed between a conductor layer (CL ) and the gate electrode ( ). Thus, the gate structures (GT and GT ) can be disposed without being restricted by the alignment margin of the contact hole (CH ), and the distance between the gates can be reduced for attaining high integration.

Method for forming a semiconductor device having a plurality of circuits parts

A semiconductor device, having a multi-layer interconnection structure, is provided which comprises a semiconductor substrate and a plurality of interlayer insulating films formed on the semiconductor substrate. A plurality of conductive leads are formed in the interlayer insulating films. In one of the interlayer insulting films having conductive lead or leads, at least one conductive plug is formed vertically to connect the conductive leads in different interlayer insulating films. Further, adjacent conductive leads may be formed in an adjacent interlayer insulating films are connected together to form a unified conductive lead.

Semiconductor device having an improved multi-layer interconnection structure and manufacturing method thereof

A transistor having a longer channel length and serving as a reference, and a transistor having a shorter channel length and to be subjected to effective channel length extraction are prepared (step ST ). A hypothetical point at which a change in a total drain-to-source resistance is estimated to be approximately zero when a gate overdrive is slightly changed is extracted in a mask channel length versus total drain-to-source resistance plane. The values of a function (F) are calculated which are defined by the difference between the rate of change in the total drain-to-source resistance and the product of a channel resistance per unit length and the rate of change in a mask channel length at the hypothetical points (step ST ). A true threshold voltage of the transistor having the shorter channel length is determined by a shift amount (&dgr;) which minimizes the standard deviation of the function (F) determined in the step ST (step ST ). A resistance-based method thus extracts an effective channel length and a series resistance with increased accuracy.

Device for evaluating characteristic of insulated gate transistor

Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of silicide structure are are provided together, and a method of manufacturing the same. Each gate electrode (,) of gate structures (GT,to GT,) is covered with an upper nitride film (,) and sidewall nitride film (,). Therefore, when an interlayer insulating film (,) being oxide film is selectively removed for forming contact holes (CH,and CH,), the upper nitride film (,) and sidewall nitride film (,) are not removed, thereby preventing the gate electrode (,) from being exposed. Particularly, in the gate structures (GT,and GT,), even when the contact hole (CH,) is dislocated to either side, no short-circuit is developed between a conductor layer (CL,) and the gate electrode (,). Thus, the gate structures (GT,and GT,) can be disposed without being restricted by the alignment margin of the contact hole (CH,), and the distance between the gates can be reduced for attaining high integration.

Semiconductor device with electrical isolation means

Semiconductor device including a plurality of interconnection layers

A first polysilicon film which contains phosphorus as an impurity is formed on a semiconductor substrate. A second polysilicon film which is higher in phosphorus concentration than the first polysilicon film is formed on the first polysilicon film. The second polysilicon film is anisotropically etched to expose a surface of the first polysilicon film. Thermal oxidation is then performed. A surface of the first polysilicon film and a surface of the second polysilicon film are oxidized according to their respective oxidization rates depending on their respective phosphorus concentrations. Thus, a semiconductor device in which the size of the gate electrode can be readily controlled and damage to the semiconductor substrate or the like can be suppressed, is obtained.

Semiconductor device with gate electrode portion and method of

An interconnection structure of a semiconductor device with a gate electrode, an active region provided in the vicinity of the gate electrode and a first buried layer in a contact hole exposing the gate electrode and the active region. The contact hole is easily formed, and the first buried layer has a substantially low interconnection resistance value.

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Tokyo, Japan

Hiroyuki Amishiro