Fujitsu Corporation

Fujitsu Microelectronics Limited

Fujitsu Semiconductor Limited

Fujitsu Limied

Hiroyoshi Tomita

Yasurou Matsuzaki

Masao Taguchi

Tatsuya Kanda

Yoshihiro Takemae

Nobutaka Taniguchi

Masao Nakano

Naoharu Shinozaki

Yasuharu Sato

Masafumi Yamazaki

Hirohiko Mochizuki

Makoto Yanagisawa

Atsushi Hatakeyama

Toshiya Uchida

Yukinori Kodama

Shinnosuke Kamata

Shusaku Yamaguchi

Hiroyuki Ogawa

Yoshinori Okajima

Takaaki Suzuki

Kenichi Kawasaki

Yasuhiro Fujii

Kotoku Sato

Kota Hara

Yoshihide Bando

Waichirou Fujieda

Hiroko Douchi

Masato Takita

Hiroyuki Kobayashi

Shinya Fujioka

Masataka Mizukoshi

Masato Matsumiya

Tadao Aikawa

Tatsushi Otsuka

Tomohiro Kawakubo

Miki Yanagawa

Tomonori Hayashi

Hidehiko Akasaki

Hiroyuki Fujimoto

Masanori Kurita

Takahiro Suzuki

Yukihiro Nomura

Toyonobu Yamada

Yuji Kurita

Masami Matsuoka

Fusao Seki

Masahiko Saitou

Masahiro Yada

Kazuhiro Ninomiya

Osamu Hirooka

A semiconductor device includes a semiconductor substrate; a memory cell array including a plurality of memory cells formed on the semiconductor substrate and arranged in a matrix in a first direction and a second direction on the surface of the semiconductor substrate; a plurality of sense amplifiers formed on the semiconductor substrate and including a first sense amplifier and a second sense amplifier; and a plurality of bit lines extending along the first direction above the memory cell array, and arranged side by side in the second direction, wherein the plurality of bit lines include a first bit line pair formed in a first wiring layer and a second bit line pair formed in a second wiring layer located above the first wiring layer.

Semiconductor device including memory cell having capacitor

An oscillation device includes a first setting unit that outputs an oscillation period designation signal, a calculating unit that performs an arithmetic operation on the oscillation period designation signal, and an oscillating unit that generates an oscillation signal having a period based on the oscillation period designation signal subjected to the arithmetic operation.

Oscillation device, method of oscillation, and memory device

An oscillating device including: an oscillator generating an oscillation signal according to an enable signal; a counter counting an oscillation number of the oscillation signal and being able to reset at the oscillation number indicated by a first signal; and a comparator comparing the counted oscillation number and a reference number, is provided.

Oscillating device, method of adjusting the same and memory

First and second data output circuits obtain corresponding parts of read data of a storage circuit to output to first and second input/output pads in a second test mode. First and second data input circuits obtain output data of the first and second data output circuits via the first and second input/output pads to output in the second test mode. A comparison object selection circuit selects output data of the first and second data input circuits to output in the second test mode. A judging circuit performs a test judgment by comparing output data of the comparison object selection circuit with expected value data and outputs a test result signal in the second test mode.

Semiconductor device and system

A semiconductor device includes a current-mirror circuit including a first ring-shape gate, a second ring-shape gate, a first diffusion layer formed around the first ring-shape gate and the second ring-shape gate, a second diffusion layer formed inside the first ring-shape gate, a third diffusion layer formed inside the second ring-shape gate, an interconnect line electrically connecting the first ring-shape gate and the second ring-shape gate to a same potential, and an STI area formed around the first diffusion layer, wherein a first transistor corresponding to the first ring-shape gate and a second transistor corresponding to the second ring-shape gate constitute the current-mirror circuit, wherein gates of dummy transistors that do not function as transistors are situated between the STI area and the first and second ring-shape gates, and are arranged both in a first direction and in a second direction substantially perpendicular to the first direction.

Semiconductor device with current mirror circuit having two transistors of identical characteristics

A multipurpose terminal receives an address signal and a data signal. An address valid terminal receives an address valid signal indicating that a signal supplied to the multipurpose terminal is the address signal. An arbiter determines which of an external access request and an internal refresh request is given priority. The arbiter disables reception of the internal fresh request in response to a fact that both a chip enable signal and the address valid signal reach a valid level (an external access request). The arbiter enables the reception of the internal refresh request in response to completion of read or write operation. As a result, in a semiconductor memory device including the multipurpose terminal which receives the address signal and the data signal, contention between the read operation and the write operation, and a refresh operation which responds to the internal refresh request is prevented, which prevents a malfunction.

Semiconductor memory device including a terminal for receiving address signal and data signal

Partial refresh information indicating enabling/disabling of a refresh operation is set according to an external input and is output as a partial set signal. A refresh request signal is output periodically corresponding to a memory block for which a refresh operation is enabled. The partial set signal is masked so as to enable a refresh operation for all of the memory blocks during a period in which the partial refresh information is changed by the external input. Thus, it is possible to prevent disabling of a refresh operation in response to a refresh request even when timing of changing the partial refresh information and timing of occurrence of the refresh request signal overlap. Consequently, the refresh operation can be executed securely, and malfunctioning of the semiconductor memory can be prevented.

Semiconductor memory, system, and operating method of semiconductor memory

The present invention detects a sense amplifier having an unbalanced characteristic. In a test method for a semiconductor memory device for detecting a sense amplifier having an unbalanced characteristic, an intermediate potential having different H and L levels from normal operation is restored in a first memory cell of a first bit line connected to a test target sense amplifier, charge quantity when the capacitance of the capacitor is small is virtually stored in the first memory cell, then the data of the first memory cell is read, and a malfunction of the sense amplifier is checked based on the presence of an error of read data.

Test method for semiconductor memory device and semiconductor memory device therefor

A semiconductor memory device that enables the reduction of the circuit scale of the antifuse write voltage generation circuit. The semiconductor memory device has a first internal power supply generation circuit that boosts an external power supply voltage to generate a first internal power supply, a memory core to which the first internal power supply is supplied, an antifuse memory for writing predetermined information, and also a write voltage generation circuit that boosts the first internal power supply to generate an antifuse write voltage.

Semiconductor memory device containing antifuse write voltage generation circuit

A semiconductor memory device that includes an input buffer being inputted a write data from outside to buffer the write data and a control circuit putting the input buffer into an inactive state during a read operation and putting the input buffer into an active state when a read mask signal is inputted thereafter is provided.

Low current consumption semiconductor memory device

A semiconductor memory device includes a timing signal circuit to generate a refresh timing signal comprised of a series of pulses, a refresh address circuit to generate a refresh address in synchronization with each pulse of the refresh timing signal, a pulse selecting circuit to assert a refresh request signal in synchronization with pulses selected from the series of pulses, and a memory core to receive the refresh address and the refresh request signal and to perform a refresh operation with respect to the refresh address in response to assertion of the refresh request signal, wherein arrangement is made to switch between a first operation mode in which the selected pulses are obtained by selecting one pulse out of every predetermined number of pulses from the series of pulses and a second operation mode in which the selected pulses are obtained by selecting consecutive pulses from the series of pulses.

Semiconductor memory device with partial refresh function

The present invention suppresses the refresh failure of a DRAM due to the dispersion of a threshold of a MOSFET. The DRAM has a first unit for recording a set value of a back bias potential to be applied to a back gate of a cell transistor and a second unit for generating a back bias potential based on the set value of the back bias potential recorded in the first unit and supplying the generated back bias potential to the back gate, wherein when a threshold of a MOSFET which has a structure identical to the cell transistor and which has been fabricated in the same process as the cell transistor is greater than a target value which the cell transistor should have, a value shallower than the back bias potential for the target value is recorded in the second unit.

Semiconductor device and fabrication method thereof

Semiconductor memory device with input buffer

A delay circuit includes: an input signal line (IN) through which an input signal is inputted; a capacitor () charged with and discharging electric charge; a first switch () connected to the input signal line and operating according to the input signal when the capacitor is to be charged with electric charge; a second switch () connected to the input signal line and operating according to the input signal when the electric charge is to be discharged from the capacitor; and a comparison circuit () comparing a voltage of the capacitor and a reference voltage to output a delay signal of the input signal.

Delay circuit having a capacitor and having reduced power supply voltage dependency

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Kawasaki, Japan

Hiroyoshi Tomita