Kabushiki Kaisha Toshiba

Hiroyoshi Murata

Yasoji Suzuki

Hirofumi Kato

Isao Abe

Itsuo Sasaki

Toshio Yanagisawa

Kazuyoshi Yamamoto

Isao Arita

Hiroyuki Hamagawa

Masakatsu Kitani

Akira Takiba

Osamu Matsumoto

Kazuyoshi Shinada

Tadashi Maruyama

Tomohisa Shigematsu

Kohei Kinoshita

Ichiro Kobayashi

Nobuo Yamasaki

Kenshi Tsuchiya

Yoshihiro Aoki

With regard to a display device having an SRAM incorporated in a pixel, a technology is disclosed, which is capable of reducing manufacturing costs by simplifying a constitution of a driver. A write voltage equivalent to white or black represented by a tone level of a normal display area is converted into a write voltage corresponding to a brightest white display or a darkest black display in the pixel, and is held in the SRAM of each pixel. In the case of normal display, display is carried out with the write voltage represented by the tone level of the normal display area. In the case of static image display, display is carried out with the write voltage corresponding to the brightest white display or the darkest black display in the pixel, the write voltage being held in the SRAM. Since the normal display and the static image display can be carried out with a write voltage supplied from one driver, the constitution of the driver can be simplified.

Display device equipped with SRAM in pixel and driving method of the same

A multi-gray level display designed to display multi-gray level images free of flicker or the like, by using a small number of voltages. The display comprises a first gray-level pattern generating circuit for generating a first gray-level pattern which acquires a gray level during m frame periods, a second gray-level pattern generating circuit for generating a second gray-level pattern which acquires another gray level during n frame periods (n is a positive integer greater than m), and a selection circuit for selecting and outputting one of the preset voltages, in accordance with an output from the first gray-level pattern generating circuit or the second gray-level pattern generating circuit when the input multi-gray level display data corresponds to a gray level of either the first gray-level pattern or the second gray-level pattern.

Multi-gray level display apparatus and method of displaying an image at many gray levels

A jitter correction circuit includes a delayed signal generator and an output circuit. A correction subject signal Ckd,is derived from multiplying a horizontal synchronization signal or a reference signal Vref. The correction subject signal includes jitters. The delayed signal generator is provided with a plurality of delay elements Fd,through Fdn which receive and delay the correction subject signal, respectively, by predetermined delay time to generate delayed signals Ckd,through Ckdn. The output circuit outputs one of the correction subject signal Ckd,and the delayed signals Ckd,trough Ckdn on the condition that it has predetermined timing relationship with the reference signal Vref.

Jitter correction circuit and a flat panel display device using the same

A display device disclosed includes a liquid crystal display panel, a signal-line driver circuit responsive to image data Data and a first clock signal CK1 for generating signals supplied to signal lines, a control signal generator circuit (12) responsive to a reference clock signal for generating and issuing first clock signal CK1 and adjustment clock signals SCK, and a delay-time adjuster circuit (14) which delays the image data by a specified time interval based on a corresponding adjustment clock signal SCK from the control signal generator circuit (12) to adjust the delay time of the first clock signal CK1 as generated by the control signal generator circuit (12) with respect to the image data Data, wherein this delay-time adjuster circuit (14) is provided with phase-locked loop or PLL circuits (16) for correction of the adjustment clock signals SCK, and a PLL circuit (34) for correction of the first clock signal CK1 being supplied to the signal-line driver circuit, thereby causing the first clock signal CK1 and the image data Data to be kept exactly in phase with each other.

Display device including a phase adjuster

A multi-gray level display designed to display multi-gray level images free of flicker or the like, by using a small number of voltages. The display comprises a first gray-level pattern generating circuit 311 for generating a first gray-level pattern which acquires a gray level during m frame periods, a second gray-level pattern generating circuit 321 for generating a second gray-level pattern which acquires another gray level during n frame periods (n is a positive integer greater than m), and a selection circuit 341 for selecting and outputting one of the preset voltages, in accordance with an output from the first gray-level pattern generating circuit 311 or the second gray-level pattern generating circuit 321 when the input multi-gray level display data corresponds to a gray level of either the first gray-level pattern or the second gray-level pattern.

Multi-gray level display apparatus and method of displaying an image at

A power supply switching circuit includes first to third MOS transistors (P1, P2 and P3) connected in series between a high-potential source and a standard-potential source. The circuit performs a switching operation using a standard-potential and at least one potential which is different from the standard-poential, and outputs plural power supply potentials. The third MOS transistor (P3) is inserted between the first and second MOS transistors (P1 and P2). The back gate of the third transistor (P3) is connected to an output terminal (OUT1) formed between the second transistor (P2) and the third transistor (P3) and prevents the formation of a current path via turned-off transistor (P1) due to the action of a parasitic diode in the first and second transistors caused by potential fluctuations.

Power supply switching circuit

A memory cell of a nonvolatile semiconductor memory device includes a P conductive type semiconductor substrate, first and second diffusion layers of an N conductivity type, formed in the substrate, a channel region formed in the surface region of the substrate, and which is located between the first and second diffusion layers, a floating gate electrode formed on the channel region, and a control gate electrode formed on the floating gate electrode. The memory cell further includes a third diffusion layer of the N conductivity type, and formed between the first layer and the channel region, the third layer having an impurity concentration lower than that of the first layer.

Nonvolatile semiconductor memory device with a double gate structure

Growing community of inventors

Saitama-ken, Japan

Hiroyoshi Murata