Elpida Memory, Inc.

Other

Hiroyasu Yoshida

Kanji Oishi

Satoshi Shinada

Katsuhiko Kimura

Naohisa Nishioka

Takayuki Watanabe

Seiichi Kato

Fumihito Ichikawa

When an update disable signal is at an inactivation level, a latch signal is activated in accordance with an active signal and a mode register set signal. When the update disable signal is at an activation level, the latch signal is activated in accordance with the active signal while being not activated in accordance with the mode register set signal. Based on the latch signal, the address signal is latched. Based on the latched address signal, an internal test signal is generated. With this structure, a target chip can be selectively controlled simply by activating the update disable signal in the target chip.

Semiconductor device having test mode and method of controlling the same

A semiconductor memory device comprises an anti-fuse, a memory circuit including memory cells, and a peripheral circuit configured to access only an area of the memory circuit selected depending on a state of the anti-fuse.

Semiconductor memory device and operating method thereof

A testing device for a semiconductor storage device which suppresses the increase in the circuit size, provides for facilitated accommodation to a test with frequent changes in the test pattern, and which improves testability of the semiconductor storage device. A plural number of holding circuits () are provided holding write data for memory cells of a memory cell array (-). The write data from the holding circuits () are written in the memory cells of the selected address. A plural number of comparators (CCMPN) are supplied with data read out from the memory cells and with data held by the holding circuits as expectation data to compare the readout data and the expectation data. The non-inverted value or the inverted value of the write data held by the holding circuits () is output as the write data to the memory cells and as expectation data to the comparators (CCMPN) depending on the value of the inversion control signal (DIM). A decision circuit () is provided which outputs an error flag based on a coincidence detection signal (MATCH) coupled to the plural comparators.

Semiconductor storage device

In a command generating circuit, operation mode signals (signals determining internal operations, such as ACTIVE, READ, WRITE, and PRECHARGE) are determined by decoding command signals /CS, /RAS, /CAS, and /WE. The operation mode signals and bank select signals (BS, BS, BS, and BS) are latched by internal clocks. Thereafter, a logical product (AND) of each of the latched operation mode signals and each of the latched bank select signals is calculated.

Command generating circuit and semiconductor memory device having the same

A fuse circuit uses an electrically writable fuse circuit and comprises a first fuse unit provided with a first electrically writable fuse, and a second fuse unit provided with a second electrically writable fuse, and the state of logical add of the states of the first and second fuse units is used as the output of the electrically writable fuse circuit in the first and second fuse units. Reliability in writing in of the fuse can be improved by using such a fuse circuit for a redundancy decoder circuit or the like.

Fuse circuit and semiconductor device using fuse circuit thereof

A testing device for a semiconductor storage device suppresses the increase in the circuit size, provides for facilitated accommodation to a test with frequent changes in the test pattern, and improves testability of the semiconductor storage device. A plurality of holding circuits are provided holding write data for memory cells of a memory cell array. (Original) The write data from the holding circuits are written in the memory cells of the selected address. A plurality of comparators are supplied with data read out from the memory cells and with data held by the holding circuits as expectation data to compare the readout data and the expectation data. The non-inverted or inverted value of the write data held by the holding circuits is output as the write data to the memory cells and as expectation data to the comparators depending on the value of the inversion control signal.

A parallel data outputting circuit equipped with a data inversion function, comprises P number of data comparator means, P number of majority decision circuits, P number of inversion flag generating means and P number of data inversion circuits, these being activated in parallel in one cycle. In generating an inversion flag indicating whether or not the parallel data are to be inverted and output in the inverted state, inversion flags are calculated from outputs of the inversion flag generating means and the inversion flag generating means of a cycle directly previous to a current cycle.

Data inversion circuit and semiconductor device

In a background-art optical disk drive, it is necessary to improve acceleration generated in an objective lens driving device in order to make an objective lens track a disk rotating at a high speed. This can be achieved either by increasing a thrust force acting on a movable body including the objective lens or by making the movable body lighter in weight. One method for increasing the thrust force is to make permanent magnets larger or use permanent magnets having a large magnetic force. However, this leads to such a problem that the unit becomes larger in size or higher in cost. In order to solve the foregoing problem, an inner yoke is disposed around a beam of light and inside the movable body of the objective lens driving device. Alternatively, an inner yoke having at least two sides substantially parallel with the radial direction of the disk and at least two sides substantially perpendicular thereto is disposed inside the movable body.

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Tokyo, Japan

Hiroyasu Yoshida