Mitsubishi Denki Kabushiki Kaisha

Hiroyasu Makihara

Kenji Kohda

Tsuyoshi Toyama

Yasuhiro Kouro

Akira Okugaki

Masahide Kaneko

A mask ROM device includes a plurality of memory cells each having an enhancement type FET having a gate electrode and first and second source/drain regions, a plurality of word lines connected to the gate electrodes, a plurality of bit lines connected to the first source/drain regions, a connection line formed above the gate electrode so as to electrically connect the first and second source/drain regions through contact holes in each of memory cells selected according to information to be stored.

Mask ROM device

A ROM includes an address transition detection circuit and a supply voltage rising detection circuit. The supply voltage rising detection circuit inhibits an operation of the address transition detection circuit until a supply voltage reaches a predetermined voltage after application of power.

Semiconductor memory device having address transition and supply voltage

A memory cell array is divided into a plurality of subregions along row and column directions. In data reading, 1-bit memory cell is selected from each of the subregions which are arranged on different rows and different columns in this memory cell array. Data are simultaneously read from the simultaneously selected memory cells. The simultaneously read data include information bits and at least one error checking bit. Only data of a 1-bit memory cell is read from one word line at the maximum. Thus, it is possible to extremely reduce a probability that two or more erroneous data bits are included in a plurality of bits of simultaneously read data even if a selected word line is defective. It is possible to execute error checking and correction in accordance with an ECC scheme, improving repairability for defective bits in a semiconductor memory device.

Semiconductor memory device with error checking and correcting function

A mask ROM having an ECC for error correction by carrying out operation according to a Hamming matrix in which all but 2 of 6 elements in one column and the other column match each other. The columns correspond to 32 data that will be provided to an external source, and the one column corresponds to the other column by 16 columns. The ECC is implemented so that one half of 32 correction signals with which exclusive ORs are to be taken with 32 data, are generated by a circuit identical to that of a circuit for generating the other half of the 32 correction signals; and the circuit for taking the exclusive ORs from one half of the 32 data and the corresponding correction signals can be used for taking exclusive ORs from the remaining half of the 32 data and the corresponding correction signals. The number of component elements for the correction signal generator and for the data correction circuit, and the number of input signal lines to the data correction circuit are reduced to a half, alleviating the circuit complexity of the entire ECC in comparison with that of a conventional one.

Semiconductor memory device having an error correction circuit and an

A sense amplifier for nonvolatile semiconductor storage devices, wherein a first reference voltage is generated from a first reference voltage generating circuit and a second reference voltage is generated from a second reference voltage generating circuit. A latch type sense amplifier is provided, which is connected to a bit line via a selection transistor. The latch type sense amplifier includes input/output terminals in two directions and serves to latch information when the input voltage at one input/output terminal is higher than the voltage at the other input/output terminal. A first gate transistor, conductive in response to the second reference voltage, is connected between the output of the first reference voltage generating circuit and the one input/output terminal for the latch type sense amplifier. A second gate transistor, conductive in response to the second reference voltage, is connected between a load and the other input/output terminal of the latch type sense amplifier.

Sense amplifier for nonvolatile semiconductor storage devices

In an output buffer circuit, two P channel MOSFET's (1, 2) are connected in parallel between a power supply terminal (16) and an output terminal (10), and two N channel MOSFET's (3, 4) are connected in parallel between the ground terminal (17) and the output terminal (10). When a normal power supply potential is applied to the power supply terminal (16), either one of the P channel MOSFET's (1, 2) or either one of N channel MOSFET's (3, 4) is turned on in response to an input signal. When a high potential is applied to the power supply terminal (16), two P channel MOSFET's (1, 2) or two N channel MOSFET's (3, 4) are turned on in response to the input signal.

Buffer circuit used in a semiconductor device operating by different

A memory cell array (100) of an EPROM includes a first data memory region (1a), a second data memory region (1b), a 2M code memory line (2a) and a 1M code memory line (2b). When both the first and the second data memory regions (1a, 1b) are normal, the EPROM may be used as a 2M bit EPROM, in which case a device code indicating that the EPROM is a 2M bit EPROM is read out from the 2M code memory line (2a). When a defective portion is present in one of the first and the second data memory regions (1a, 1b), the EPROM may be used as a 1M bit EPROM, in which case a device code indicating that the EPROM is a 1M bit EPROM is read out from the 1M code memory line (2b).

Semiconductor memory device having means for repairing the memory device

In an output buffer circuit, two P channel MOSFET's (1, 2) are connected in parallel between a power supply terminal (16) and an output terminal (10), and two N channel MOSFET's (3, 4) are connected in parallel between the ground terminal (17) and the output terminal (10). When a high potential is applied to the power supply terminal (16), either one of the P channel MOSFET's (1, 2) or either one of N channel MOSFET's (3, 4) is turned on in response to an input signal. When a normal power supply potential is applied to the power supply terminal (16), two P channel MOSFET's (1, 2) or two N channel MOSFET's (3, 4) are turned on in response to the input signal.

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Hyogo, Japan

Hiroyasu Makihara