Kawasaki Steel Corporation

Kawasaki Microelectronics, Inc.

Hiroyasu Kunitomo

Ryuji Ariyoshi

Isamu Kuno

Yoshihide Tada

Tomoaki Nimura

A semiconductor integrated circuit that includes a circuit element with a reduced parasitic capacitance and has a short start-up time. A well of the different type of conduction from that of the substrate is formed in the area of the surface of the semiconductor substrate under the circuit element. A constant voltage, which biases the junction between the well and the semiconductor substrate in a reverse direction, is applied to the well through a resistor having a higher impedance compared with the impedance of the capacitance of the reverse-biased junction between the well and the substrate at the frequency of the signal applied to the circuit element.

Semiconductor integrated circuit having a reduced parasitic capacitance and short start-up time

A projection is formed in a substrate by anisotropic etching and a transistor is contained in the projection. The central portion of the projection covered with a gate electrode is formed as a channel region, and drain and source regions are formed on both sides of the projection by oblique ion implantation with the gate electrode as a mask. Formed below the drain, source, and channel regions is an element isolation section having the composition of the substrate intact. This eliminates the need for an oxide insulating layer below the transistor for easy manufacturing. Carriers generated in the channel region by ionization by collision can also be discharged to the substrate.

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Chiba, Japan

Hiroyasu Kunitomo