Denso Corporation

Nippondenso Co., Ltd.

Hiroyasu Itou

Toshio Sakakibara

Akihiko Teshigahara

Mitsutaka Katada

Akiyoshi Asai

Hidetoshi Muramoto

Kunihiro Onoda

Ryuichirou Abe

Takanori Simamoto

Tosiyuki Morisita

Hideya Inagaki

A high-reliability power composite integrated semiconductor device uses thick copper electrodes as current collecting electrodes of a power device portion to resist wire resistance needed for reducing ON-resistance. Furthermore, wire bonding connection of the copper electrodes is secured, and also the time-lapse degradation under high temperature which causes diffusion of copper and corrosion of copper is suppressed. Still furthermore, direct bonding connection can be established to current collecting electrodes in the power device portion, and also established to a bonding pad formed on the control circuit portion in the control circuit portion. A pad area at the device peripheral portion which has been hitherto needed is reduced, so that the area of the device is saved, and the manufacturing cost is reduced.

Power composite integrated semiconductor device and manufacturing method thereof

A memory transistor of an EEPROM has a floating gate electrode of a shape such that it covers the entirety of a tunnel film and a channel region and does not cover a region between the channel region and an embedded layer. And, a control gate electrode is formed on an interlayer insulating film on the floating gate electrode into a shape such that it is wider than the floating gate electrode above the tunnel film, and is narrower than the floating gate electrode above the channel region.

EEPROM and EEPROM manufacturing method

In a manufacturing process of an SOI structure semiconductor device in which an MOS capacitor is located on an SOI substrate, the capacitor insulating film of the MOS capacitor is prevented from degrading due to a bimetal effect, which is caused by a thermal treatment and characteristic to the SOI substrate. A trench is formed to surround the MOS capacitor in the SOI substrate, thick oxide films are formed on sidewalls defining the trench, and the trench is filled with polysilicon to complete a trench isolation layer. Because the thick oxide films have a coefficient of thermal expansion that is different from that of a silicon semiconductor layer of the SOI substrate, the thick oxide films are able to prevent the capacitor insulating film from degrading in film quality due to the thermal treatment in the manufacturing process. As a result, an SOI semiconductor device in which an MOS capacitor on an SOI substrate offers performance comparable to an MOS capacitor on a silicon substrate can be formed.

Semiconductor device and method for manufacturing it

An island region surrounded by a trench is provided in an SOI substrate. The island region is further surrounded by a buffer region with a buffer region contact layer. In the island region, a source region is annularly provided around a drain region, and source and drain electrodes are respectively provided on the source and the drain regions. An annular auxiliary electrode is formed with the source electrode to extend over the trench. Accordingly, a voltage applied to the source electrode can be applied to the auxiliary electrode, so that electric field concentration between the buffer region and the source electrode is relaxed.

Semiconductor apparatus having high withstand voltage

An improved manufacturing method for a semiconductor device, which can reduce process inductive fault such as oxidation inductive stacking fault (OSF) and contribute to the improvement of the electric characteristics of the semiconductor device, is disclosed. A thermal oxide film is formed on a semiconductor substrate, then a nitride film is formed and a medium temperature heat treatment is provided to the semiconductor substrate within a temperature range from 600.degree. C. to 1,000.degree. C., whereby an interstitial oxygen concentration can be lowered. Subsequently, ion implantation, etc. are provided as a well region forming process, and a drive-in process is performed by means of a high temperature heat treatment. At this time, ion implantation dose is set to 9.times.10.sup.13 �cm.sup.-2 ! or less, and the temperature of the heat treatment is lowered or the duration of the teat treatment is shortened. After this, an element separation layer process is performed, and a gate oxide film, a gate electrode, a source/drain layer, a CVD oxide film, a contact hole and a metal wire are formed.

Method for making FET having reduced oxidation inductive stacking fault

An LOCOS film is formed on an Si substrate, a gate oxide film and a gate electrode are formed thereon, and source/drain impurities are ion implanted into the Si substrate using the gate electrode as a mask. Then, a BPSG film is formed at a film density of 1.8 g/cm.sup.3 or more. A recessed part is formed in the BPSG film by the first photolithographic process with an etching depth of 20% or more but under 100% of the thickness of the BPSG film. Thereafter, the BPSG film is fluidized by reflow treatment to shape a part which is to be a contact hole into a funnel with an 'upwards convex' curvature. Finally, the part formed into the funnel is etched to make a contact hole. As a result, wiring disconnection within the contact hole can be prevented, the diffusion depth controllability for the source/drain impurities can be improved, and the fall in the impurity density in the source/drain surface can be prevented.

Growing community of inventors

Nagoya, Japan

Hiroyasu Itou