Other

Renesas Electronics Corporation

Renesas Technology Corp.

Hiroyasu Ishizuka

Kazuo Tanaka

Kousuke Okuyama

Naozumi Morino

Kazuo Sakamoto

Katsuhiko Kubota

Akihiro Shimizu

Masahiro Moniwa

Keizo Kawakita

Mitsugu Kusunoki

Yasuhiko Kawashima

Yoshiyasu Tashiro

Takeo Toba

Nobuhiro Kasa

Kayoko Saito

Chiemi Hashimoto

Shinichiro Masuda

A semiconductor integrated circuit device with a 'PAD on I/O cell' structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor chip. When seen in a plan view of the I/O part, a resistance lies above the transistor and a first and a second diode lie above the resistance; a second transistor lies above the diodes; and a logic block lies above the second transistor with a pad lead part, for example, formed in a metal wiring layer, therebetween. This permits the pad through the second transistor to be on the same node and therefore the pad lead part can be disposed almost in the center of the I/O part.

Semiconductor integrated circuit device having an NMOS with a high resistance drain terminal

A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.

Semiconductor integrated circuit device

A protection circuit with suppressed erroneous operation due to power source fluctuation has a first resistor and a capacitor connected in series between a power source line and a ground line, an inverter with an input connected between the first resistor and the capacitor, and a MOS transistor with a gate electrode that receives an output of the inverter and with a drain electrode and source electrode connected to the power source line and the ground line. When high voltage fluctuation occurs in the power source line, a level change at a connection point between the first resistor and the capacitor is delayed according to a time constant. By the delay, the MOS transistor that receives an output of the inverter is temporarily turned on and discharges a high voltage to the ground line.

Semiconductor integrated circuit

A protection circuit with suppressed erroneous operation due to power source fluctuation has a first resistor and a capacitor connected in series between a power source line and a ground line, an inverter with an input connected between the first resistor and the capacitor, and a MOS transistor with a gate electrode that receives an output of the inverter and with a drain electrode and source electrode connected to the power source line and the ground line. When a high voltage fluctuation occurs in the power source line, a level change at a connection point between the first resistor and the capacitor is delayed according to a time constant. By the delay, the MOS transistor that receives an output of the inverter is temporarily turned on and discharges a high voltage to the ground line.

A first clamp circuit and a second clamp circuit stacked thereon in vertical respectively for clamping unwanted level voltages are provided between the high potential side power source and low potential side power source and an intermediate node formed by vertical stacking of the first clamp circuit and second clamp circuit is coupled with the power source for internal circuit. Since a capacitor originally provided in the internal circuit is allocated in parallel to the first clamp circuit, impedance is reduced due to existence of the capacitor and potential difference due to over-current flowing in the chip is reduced. Accordingly, potential difference due to over-current flowing into the chip may be reduced and static electricity dielectric strength can be improved by allowing higher over-current. Thereby, impedance when the clamp circuits are stacked in two stages.

In order to eliminate the difference in ESD resistance caused by polarities of excessive voltages applied to an external terminal and enhance ESD resistance of a semiconductor integrated circuit device to both the positive and negative overvoltages, a protection element having a thyristor structure, for protecting an internal circuit from the positive overvoltage and a protection element made up of a diode D for protecting the internal circuit from the negative overvoltage are provided between the external terminal and a ground potential.

Semiconductor integrated circuit device and method of manufacturing the same

Disclosed are a semiconductor integrated circuit device and a method of manufacturing the same capable of realizing the two-level gate insulator process for the DRAM without increasing the number of manufacturing steps and that of photomasks. After forming a gate electrode of a MISFET which constitutes a memory cell in a memory array region on a semiconductor substrate, the substrate is subjected to thermal treatment (re-oxidation process). At this time, since bird's beak of the thick gate insulating film formed below the sidewall portion of the gate electrode penetrates into the center of the gate electrode, a gate insulating film thicker than the gate insulating film before the re-oxidation process is formed just below the center of the gate electrode. Meanwhile, since the gate electrode in the peripheral circuit region has a gate length longer than that of the gate electrode in the memory array region, the thickness of the gate insulating film just below the center thereof is almost equal to that before the re-oxidation process.

Semiconductor integrated circuit device and manufacturing method thereof

Disclosed herein is a semiconductor device wherein a thyristor protective element and a trigger element are provided in a semiconductor layer formed on a buried insulating layer, and a trigger electrode (gate) of the thyristor protective element and a back gate of the trigger element are provided in the same p well and electrically connected to each other to thereby drive the thyristor protective element based on a substrate current produced by the breakdown of the trigger element.

Semiconductor device and the process of manufacturing the semiconductor device

In order to eliminate a difference in ESD resistance caused by the polarities of excessive voltages applied to an external terminal and enhance the ESD resistance of a semiconductor integrated circuit device to both positive and negative overvoltages, a protection element having a thyristor structure, for protecting an internal circuit from the positive overvoltage and a protection element made up of a diode D1 for protecting the internal circuit from the negative overvoltage are provided between the external terminal and a ground potential.

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Ome, Japan

Hiroyasu Ishizuka