Seiko Epson Corporation

Hiroyasu Honda

Tomonaga Hasegawa

Yukinari Shibata

Mihiro Nonoyama

Yoshiro Iwasa

Keitaro Fujimori

Yoshiteru Ono

A data transfer control device including: a link controller which analyzes a packet received through a serial bus; a packet detection circuit which detects completion or start of packet reception based on analysis result of the received packet; first and second packet buffers into which the packet received through the serial bus is written; and a switch circuit which switches a write destination of the received packet. When a Kth packet has been written into one of the first and second packet buffers and completion of reception of the Kth packet or start of reception of a (K+1)th packet subsequent to the Kth packet has been detected, the switch circuit switching the write destination of the (K+1)th packet to the other of the first and second packet buffers.

Data transfer control device including a switch circuit that switches write destination of received packets

A data transfer control device includes: a link controller which analyzes a packet received from a host-side data transfer control device through a serial bus; and an interface circuit which generates interface signals and outputs the generated interface signals to an interface bus. A packet transferred from the host-side data transfer control device through the serial bus includes a synchronization signal code field for setting a synchronization signal code. The interface circuit generates synchronization signals FPFRAME and FPLINE included in the interface signals based on the synchronization signal code set in the packet.

Data transfer control device and electronic instrument

A data transfer control device includes: an interface circuit to which data of which one data unit is K bits is input through an interface bus; and a link controller which generates a packet transmitted through a serial bus. The link controller includes: a data formatter which generates (N&#xd7;I)-byte packed data containing M pieces of (K+L)-bit data obtained by adding L bits of dummy data to the K-bit data, the data formatter generating the packed data in which L and M are variably set corresponding to K; and a packet generation circuit which generates a packet in which the packed data is inserted in a data field.

A data transfer control device including: a link controller which analyzes a received packet transferred from a host-side data transfer control device through a serial bus; an interface circuit which generates an interface signal and outputs the generated interface signal to an interface bus; and an internal register in which is set timing information for specifying a timing at which a signal level of the interface signal output from the interface circuit changes. The interface circuit generates the interface signal, a signal level of which changes at a timing according to the timing information set in the internal register.

A data transfer control device includes a link controller which analyzes a packet received from a host-side data transfer control device through a serial bus, and an interface circuit which generates an interface signal and outputs the generated interface signal to an interface bus. When the address automatic update mode in an address automatic update field of a packet received from the host-side data transfer control device is set to ON, the interface circuit sequentially outputs signals of automatically updated addresses and signals of L-bit-data from among K bits of data set in the packet, the L-bit-data making a pair with each of the automatically updated addresses, while performing address automatic update processing M times (K=L&#xd7;(M+)) using an address set in the packet as a start address.

Data transfer control device and electronic instrument having reduced power consumption

A data transfer control device including: a link controller which analyzes a packet received through a serial bus and generates a packet to be transmitted through the serial bus; an interface circuit which performs interface processing between the data transfer control device and a display driver connected to the data transfer control device through an interface bus; and a signal detection circuit which detects a vertical synchronization signal VCIN used for indicating a non-display period of a display panel and outputs a detection signal VDET. When the link controller has received a read request packet which requests reading of status of the VCIN, the link controller waits for the VDET to be output, and performs processing of transmitting a response packet through the serial bus on condition that the VDET has been output.

A data transfer control device includes: a link controller which analyzes a packet received through a serial bus; an interface circuit which generates interface signals and outputs the interface signals to an interface bus; and a reset signal output circuit which outputs a reset signal to the interface circuit. The link controller analyzes a packet to determine whether or not the received packet includes synchronization signal generation direction information (synchronization signal code). The reset signal output circuit outputs the reset signal to the interface circuit when the link controller has determined that the received packet includes the synchronization signal generation direction information.

A data transfer control device includes a transceiver which receives a request packet from a partner device connected through the serial bus, and a link controller which analyzes the received request packet. The link controller reads an address size value set in the address size field of the received request packet, omits reading of an address from the address field when the address size value set in the address size field is zero, and reads an address, size of which is indicated by the set address size value from the address field when the address size value set in the address size field is other than zero.

A data transfer control device including: a link controller which analyzes a received packet transferred from a host-side data transfer control device through a serial bus; an interface circuit which generates interface signals and outputs the generated interface signals to an interface bus; and an internal register in which is set interface information for specifying signal types of the interface signals output from the interface circuit. The interface circuit includes first to Nth interface circuits (N is an integer greater than one), and each of the first to Nth interface circuits generates an interface signal of a signal type according to the interface information set in the internal register.

Data transfer control device and electronic instrument generating interface signal of signal type according to interface information set in internal register

A flexible substrate including: a first part provided with a first device DV; a second part provided with a second device; a wiring part placed between the first part and the second part and including a plurality of wirings for coupling the first device and the second device; the first device including at least a first data transfer control unit, the second device including at least a second data transfer control unit, the first data transfer control unit and the second data transfer control unit transferring data by using a differential signal, and the plurality of wirings for coupling the first device and the second device including at least one differential signal line pair for transferring data by using a differential signal.

Flexible substrate and electronic equipment

In a bi-level displaying device, dither signal trains Y.sub.0 to Y.sub.15 for displaying half tone levels are generated from signal trains for basic tone levels X.sub.0 to X.sub.16 and from a 1/2 dither pattern constituted by the same numbers of dots having different threshold values. Dither signal trains Z.sub.0 Z.sub.31 for displaying unequally divided intermediate tone levels are generated by the basic trains X.sub.0 to X.sub.16 from a 1/4 dither pattern and a 3/4 dither pattern which are associated with unequal numbers dots having the different threshold values. Since the unequally divided intermediate tone levels can be displayed easily, it becomes possible to get natural intermediate tone levels. A dither pattern having a reversed pattern is adopted so that twice the number of intermediate tone levels can be displayed. Hence, a total of 64 tone levels can be displayed to produce images with fine detail and high resolution.

Growing community of inventors

Chino, Japan

Hiroyasu Honda