Hitachi, Ltd.

Renesas Technology Corp.

Elpida Memory, Inc.

Nec Corporation

Renesas Eastern Japan Semiconductor, Inc.

Hiroya Shimizu

Hideo Miura

Ryuji Kohno

Asao Nishimura

Hideki Tanaka

Tatsuya Nagata

Tosiho Miyamoto

Masatoshi Kanamaru

Toshio Miyatake

Mitsuaki Katagiri

Hideyuki Aoki

Yoshishige Endo

Satoshi Isa

Naoto Ban

Yuji Wada

Atsushi Hosogane

Masaaki Namba

Hiroshi Ikeda

Yasushi Takahashi

Satoshi Nakamura

Hideaki Takahashi

Toshio Sugano

Seiji Narui

Takashi Suga

Takanori Aono

Yukitoshi Hirose

Fumiyuki Osanai

Hideshi Fukumoto

Satoshi Itaya

Masaharu Imazato

Kensuke Tsuneda

Takashi Iida

A semiconductor device has a semiconductor chip in which a plurality of semiconductor components and a plurality of pads are arranged, a plurality of external connection contacts arranged in grids, and a plurality of wires for electrically connecting the pads and the external connection contacts. The pads include a plurality of pad groups including a pair of electrode pads connected to the plurality of semiconductor components in common and a plurality of signal pads respectively connected to the semiconductor components connected to the electrode pads. In each pad group, each signal pad is arranged adjacently to one of the electrode pads; and each wire extending from each signal pad is extended along a wire extended from the electrode pad adjacent to each signal pad.

Fine pitch grid array type semiconductor device

System, method and program for inductance analysis for reducing time for analysis, to cope with increase in the system size, to achieve high accuracy in the analysis. Information on a power supply plane, in a state in which a beginning point of non-coupled current of return current accompanying a signal current is placed in the vicinity of a signal through-hole on the power supply plane, based on position information of said signal through-hole, is received. Potential distribution in the power supply plane is determined and output. The non-coupled inductance from the signal through-hole to the power supply through-hole in the power supply plane is evaluated. In the potential analysis, non-coupled inductance L from the signal through-hole to the power supply through-hole is represented by resistance R. The relationship that a voltage increment &#x394;V is represented by the product of the non-coupled inductance L and the rate of time change of the current, &#x394;V=L&#x394;I/&#x394;t, is replaced by the relationship that the voltage V is represented by the product of resistance R and non-coupled current I, V=R&#xd7;I. Potential analysis is performed by analyzing two-dimensional heat diffusion in the power supply plane assuming that a heat source is placed at a beginning point of the non-coupled current.

Inductance analysis system and method and program therefor

A method for designing a device that comprises a first semiconductor chip, a second semiconductor chip and an adjustment target is disclosed. The first semiconductor chip comprises an input pad, a first power supply pad and a first ground pad. The second semiconductor chip comprises an output pad coupled to the input pad. The adjustment target is connected to the first and the second semiconductor chips. A main target variable is calculated from an input circuit chip model, an output circuit chip model of the second semiconductor chip in frequency domain and a target impedance model of the adjustment target in frequency domain. The input circuit chip model is created by representing the first semiconductor chip in frequency domain in consideration of a first capacitor model between the input pad and the first power supply pad, a second capacitor model between the input pad and the first ground pad, and a chip internal capacitor model between the first power supply pad and the first ground pad. The main target variable is compared with a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.

Method for designing device, system for aiding to design device, and computer program product therefor

In a memory module, reference potential connecting patterns are disposed on high frequency signal lines and/or on the extension lines extending from the terminal ends of the signal lines as well as a shield cover for covering semiconductor memory chips is disposed on the substrate, and the reference potential connecting patterns are connected to the shield cover through metal cover contact parts.

Semiconductor device, noise reduction method, and shield cover

A semiconductor device is provided which includes a semiconductor element having power pads for supplying a power potential, ground pads for supplying a ground potential, and signal pads for inputting and outputting a signal, all of which are formed on one main surface thereof. Power bumps for outside connection are connected with the power pad by power wiring sections, ground bumps for outside connection are connected with the ground pad by ground wiring sections, and signal bumps for outside connection are connected with the signal pad by signal wiring sections. The power wiring sections or the ground wiring sections are respectively located adjacently on both sides of the signal wiring sections and the power wiring sections are respectively located adjacently on sides of the ground wiring sections.

Semiconductor device

A semiconductor device including a semiconductor element having external terminals at a first level and external electrodes at a second level, higher than the first level. The external terminals include power terminals, ground terminals and signal terminals formed on a main surface of the semiconductor element. The external electrodes include power electrodes connected to the power terminals via power connecting sections, ground electrodes connected to the ground terminals via ground connecting sections and signal electrodes connected to the signal terminals via signal connecting sections. One of the signal terminals, signal electrodes and corresponding signal connecting sections are surrounded by either the power connecting sections connecting the power terminals and power electrodes or by the ground connection sections connecting the ground terminals and ground electrodes.

A probe structure is provided in which secondary electrodes of a main base material and probes are formed can be electrically connected to electrodes in a substrate side even when a lot of probes are formed in a large area, so that a lot of LSIs within a wafer can be tested in one lot in a wafer test process, and an efficiency of the test process can be improved. In the probe structure, an interposer constituted by a high rigid material is arranged between the main base material having the probes formed therein and the substrate side, and the secondary electrodes of the main base material having the probes formed therein are electrically connected to the electrodes in the substrate side via the interposer.

Probe structure

A method of manufacturing a semiconductor device has forming process for forming a semiconductor device on a major surface of a wafer, and testing process for testing defect of the semiconductor device formed on the wafer. The testing process includes a step bringing a testing apparatus into contact with test electrodes of the semiconductor device. The testing apparatus has a contactor including a plurality of probes that come into contact with the test electrodes of the semiconductor device to be tested, and secondary electrodes electrically connected to the probes and disposed on a surface opposite to the probes; a substrate on which electrodes electrically communicated to the contactor by a conducting device. The conducting device is so formed that stress applied to the conducting device in the state where the probes are in contact with the test electrodes is larger than stress applied to the conducting device in the state where the probes are not in contact with the test electrodes.

Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device has forming process for forming a semiconductor device on a major surface of a wafer, and testing process for testing defect of the semiconductor device. The testing process includes bringing a testing apparatus into contact with test electrodes of the semiconductor device. The testing apparatus has a contactor including probes that come into contact with the test electrodes of the semiconductor device, and secondary electrodes electrically connected to the probes and disposed on a surface opposite to the probes; and a substrate on which electrodes electrically communicated to the contactor by a conducting device. The conducting device is so formed that stress applied to the conducting device in the state where the probes are in contact with the test electrodes is larger than stress applied to the conducting device in the state where the probes are not in contact with the test electrodes.

Testing apparatus for carrying out inspection of a semiconductor device

A semiconductor device includes a quadrangular semiconductor substrate and a self test circuit formed on the semiconductor substrate. A plurality of pads are formed on the semiconductor substrate, which pads are coupled at least to the self test circuit. The semiconductor substrate includes four rectangular or square regions which each include a respective corner of the quadrangle, and at least two of the pads are respectively located on diagonally opposite ones of the regions from one another.

Semiconductor device and test device for same

A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.

Packaging device for holding a plurality of semiconductor devices to be inspected

Since each wiring line is formed on one surface of the associated beam at a prescribed width over the entire length of the beam, the beam has the same sectional shape taken in the width direction at any point along an arbitrary longitudinal direction of the beam. As a result, the second moment of area, which is determined by the shapes of the beam and the wiring line, is uniform. This prevents a problem of the curvature of a beam varying locally when the beam is bent by a prescribed amount due to contact of the probe with a pad of a subject body. This, in turn, prevents local concentration of stress in the beams and thereby prevents breakage of the beam. Therefore, the probe structure can be miniaturized while the strength of the beams is kept at a required level, whereby a semiconductor device testing apparatus capable of accommodating many probes can be realized.

Semiconductor device testing apparatus and semiconductor device manufacturing method using it

A semiconductor device testing apparatus is realized, which allows contactors to be positioned throughout the wafer surface highly accurately for uniform contact, testing a large-sized wafer, and cost reduction. A plurality of divided contactor blocks is formed with a positioning groove. The groove is used to position the plurality of contactor blocks with a positioning frame. Because the contactor blocks are divided into plurals, it is less likely that a partial surface distortion affects other portions to impair surface flatness as compared with the case where a plurality of non-divided contactors is formed integrally, and the plurality of contactor blocks can be brought into contact with a wafer to be tested uniformly. Additionally, even though abnormality is generated in a part of the contactor blocks, only the part of the contactor blocks is replaced. Therefore, replacement costs can be reduced as compared with the case where a plurality of non-divided contactors is formed integrally.

Semiconductor device testing apparatus and method for manufacturing the same

A semiconductor device is provided which is highly reliable and operable at fast speed and low noises. In this semiconductor device, there are provided a power wiring section , a ground wiring section and a signal wiring section are formed on one level. The power wiring section or the ground wiring section is formed adjacently on both sides of at least one part of the signal wiring section.

Growing community of inventors

Ryugasaki, Japan

Hiroya Shimizu