Sanyo Electric Co., Ltd.

Other

Kanto Sanyo Semiconductors Co., Ltd.

Gifu Sanyo Electronics Co., Ltd.

Hirotoshi Kubo

Hiroaki Saito

Eiichiroh Kuwako

Masahito Onda

Masanao Kitagawa

Shouji Miyahara

Hiroyasu Ishida

Mitsuo Umemoto

Koujiro Kameyama

Hiroki Etou

Makoto Oikawa

Shigehito Matsumoto

Yukari Shirahata

Masamichi Yamamuro

Shigeyuki Murai

Hisaaki Tominaga

Masamichi Yanagida

Satoshi Iwata

Yasuhiro Igarashi

Masahiro Shibuya

Hidetaka Sawame

Hiroaki Saitou

Keita Odajima

Masato Onda

Junichiro Tojo

Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to a grounding potential are connected to the backside electrode through feedthrough electrodes penetrating the semiconductor substrate in a thickness direction.

Semiconductor device and method of manufacturing the same

An interlayer dielectric film is completely buried in a trench, and failures caused by step coverage is prevented because a source electrode can be formed substantially uniformly on an upper portion of a gate electrode. Also, in the processes of forming a source region, a body region and an interlayer dielectric film, only one mask is necessary so that the device size is reduced to account for placement error of only one mask alignment.

Insulated gate-type semiconductor device and manufacturing method of the same

A power MOSFET comprises: a semiconductor substrateof a first conduction type; a drain layerof the first conduction type and formed on a surface layer of the substrate; a gate insulating filmformed in a partial region on the drain layer; a gate electrodeformed on the gate insulating film; an insulating filmformed on the gate electrode; a side wall insulatorformed on side walls of the gate insulating film, the gate electrode, and the insulating film; a recess formed on the drain layerand in a region other than a region where the gate electrodeand the side wall insulatorare formed; a channel layerof a second conduction type opposite to the first conduction type and formed in a range from the region where the recess is formed to a vicinity of the region where the gate electrodeis formed; a source region layerof the one conduction type and formed on the channel layeroutside the recess; and a wiring layerformed to cover the channel layerwhich is exposed through the recess, the side wall insulator, and the insulating film.

Semiconductor device and a method of fabricating the same

In a MOSFET, after an element region is formed, a wiring layer is formed subsequently to a barrier metal layer, and hydrogen annealing is performed. However, in the case of an n-channel MOSFET, a threshold voltage is lowered due to an occlusion characteristic of the barrier metal layer. Thus, an increased impurity concentration in a channel layer causes a problem that reduction in an on-resistance is inhibited. According to the present invention, after a barrier metal layer is formed, an opening is provided in the barrier metal layer on an interlayer insulating film, and hydrogen annealing treatment is performed after a wiring layer is formed. Thus, an amount of hydrogen which reaches a substrate is further increased, and lowering of a threshold voltage is suppressed. Moreover, since an impurity concentration in a channel layer can be lowered, an on-resistance is reduced.

Method for manufacturing semiconductor device

A capacity layer is formed of non-doped polysilicon. Unlike capacity layers formed of an oxide film, generation of seams and the like can be suppressed and thereby a stable capacity layer can be formed. Moreover, polysilicon used as a capacity layer may be doped polysilicon, and an oxide film formed on the surface of the polysilicon also serves as a capacity film. Thus, provision of an insulated gate device featuring low capacity is made possible.

Insulated gate semiconductor device and manufacturing method of the same

When Ti as a barrier metal layer is brought into contact with a diffusion region of boron provided on a surface of a silicon substrate, there is a problem that boron is absorbed by titanium silicide, and contact resistance is increased. Although there is a method of additionally implanting boron whose amount is equal to the amount of boron absorbed by titanium silicide, there has been a problem that when boron is additionally implanted into, for example, a source region in a p-channel type, the additionally added boron is diffused deeply at the diffusion step, and characteristics are deteriorated. According to the invention, after formation of an element region, boron is additionally implanted into the whole surface at a dosage of about 10% of an element region, and is activated in the vicinity of a surface of a silicon substrate by an alloying process of a barrier metal layer. By this, a specified concentration profile of the element region is kept, and the impurity concentration only in the vicinity of the surface can be raised. Accordingly, even if boron is absorbed by titanium silicide, a specified boron concentration can be kept in the element region, and the increase of contact resistance can be suppressed.

Manufacturing method of semiconductor device

Conventional power MOSFETs enables prevention of an inversion in a surrounding region surrounding the outer periphery of an element region by a wide annular layer and a wide sealed metal. Since, resultantly, the area of the surrounding region is large, increase in the element region has been restrained. A semiconductor device is hereby provided which has an inversion prevention region containing an MIS (MOS) structure. The width of polysilicon for the inversion prevention region is large enough to prevent an inversion since the area of an oxide film can be increased by the depth of the trench. By this, leakage current can be reduced even though the area of the region surrounding the outer periphery of the element region is not enlarged. In addition, since the element region is enlarged, on-state resistance of the MOSFET can be reduced.

Semiconductor device with peripheral trench

In a conventional power MOSFET, an electric field concentration occurs at a gate electrode bottom portion on the outermost periphery of an operating area, thereby causing a deterioration in high voltage strength between the drain and the source, or between the collector and emitter. In this invention, a trench at the outermost periphery of an operating area is shallower than trenches of the operating area. Thereby, the electric field concentration at the gate electrode bottom portion on the outermost periphery of the operating area is relieved, and a deterioration in high voltage strength between the drain and source is suppressed. Furthermore, by narrowing the outermost peripheral trench aperture portion, trenches different in depth can be formed by an identical step.

Method of manufacturing semiconductor device

Semiconductor device with vertical transistors

This invention provides a semiconductor device which is excellent in high-frequency characteristics, wherein emitter diffusion is performed by a trench formed in a base region, the base resistance is further reduced, and the base-emitter capacitance is also reduced. A base electrode layer makes a contact with the whole surface of the base region. A tapered trench is provided in the base region. A finer emitter region is formed by emitter diffusion from the bottom portion of the trench. Since the base electrode is formed adjacently to the trench, the distance between an active region of the base and the base electrode layer can be shortened and a larger grounded area of a base can also be obtained, therefore the base resistance can be substantially reduced. In addition, by forming a fine region, the base-emitter capacitance between the base and emitter can also be reduced, therefore a transistor excellent in high-frequency characteristics can be obtained.

Semiconductor device and manufacturing method thereof

The present invention is intended to form the adjacent trenches by bending them to make a widened portion and a narrowed portion on the substrate of the semiconductor inside the trenches shaped in stripes and to arrange the adjacent widened portions and the narrowed portions alternately to lay the body contact region in the widened portion. By this arrangement, the stability of the potential is improved and thus leakage current is decreased. Further, the on-state resistance can be decreased and an advantage in rule is achieved while improving the channel width per unit area.

Insulated gate field effect semiconductor device

The invention relates to a power MOSFET and reduction of the number of mask steps in a process of fabricating the power MOSFET. The increase of a parasitic capacitance due to the reduction is suppressed. In place of a thick insulating film , a gate insulating film is formed on the entire surface of a semiconductor substrate. The gate-drain parasitic capacitance which uses the gate insulating film as a dielectric is suppressed by forming a removal region EL.

The cell density of power MOSFET used as a switch is determined by the width of the trench formed in the device, the processing limit of which is limited by the spatial resolution of the exposure apparatus used in the photolithographic process. This invention provides a method of manufacturing such devices which overcomes the processing limitation imposed by the exposure apparatus, and doubles the cell density and reduces the input capacitance for further reducing the on-state resistance and improving the switching speed. By forming a second CVD oxide film over a first oxide film defining the opening for forming a trench and subsequent anisotropic RIE etching of the second film, a side-wall film is added to the mask pattern, which promotes a further reduction of the width of the trench by more than one half.

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Gunma, Japan

Hirotoshi Kubo