Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Hiroto Nakai

Masamichi Asano

Hideo Kato

Kaoru Tokushige

Tomoharu Tanaka

Hiroshi Iwahashi

Kenichi Maeda

Yoshiyuki Tanaka

Riichiro Shirota

Yoshihisa Iwata

Seiichi Aritome

Yasuo Itoh

Yutaka Okamoto

Masaki Momodomi

Hideko Odaira

Takashi Mori

Toshio Yamamura

Isao Sato

Hiroyuki Sakamoto

Kazuhisa Kanazawa

Shigeru Kumagai

Masahiro Ishiyama

Atsushi Kunimatsu

Tatsunori Kanai

Arata Miyamoto

Noboru Shibata

Haruki Toda

Susumu Fujimura

Hirofumi Inoue

Hiroki Kudo

Hiroshi Nozue

Yuuichi Tatsumi

Hidenobu Minagawa

Mizuho Imai

Masaki Miyagawa

Kazuto Suzuki

Kazuhiro Kawagome

Shinichi Kikuchi

Hideki Mimura

Yuji Nagai

Shinya Murai

Tadashi Miyakawa

Hiroshi Nakamura

Yosuke Bando

Tsutomu Owa

Mari Takada

Yujen Lai

Shigeru Matsuda

Tsutomu Unesaki

Reina Nishino

Nobuaki Hiraga

Seiji Miyata

A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.

Memory management device predicting an erase count

According to one embodiment, a storage unit, a management unit that acquires attributes of communication apparatuses from a plurality of the communication apparatuses and stores identifiers of the communication apparatuses and the attributes in the storage unit in association with each other as communication apparatus information, and a selection unit that selects a distributor apparatus that is the communication apparatus distributing a content to the other communication apparatuses as a radio signal based on the communication apparatus information are included.

Data processor, content distribution system, and communication apparatus

According to one embodiment, a communication apparatus includes an operation mode storage unit that stores a mode in which the communication apparatus operates as a wireless base station or a terminal and a non-volatile memory, wherein a transmission message is output to the outside when the communication apparatus operates as the wireless base station, data included in a received reception message is stored in the non-volatile memory when the communication apparatus operates as the terminal, and when the communication apparatus operates as the wireless base station, after all data transmitted from a first external wireless base station is received, if a communication quality with the first wireless base station is less than a predetermined value, and no message is received from a wireless base station other than the first wireless base station, a channel selection and switching process is performed, and then the operation mode is changed from the terminal to the wireless base station.

Communication apparatus and communication method

According to the embodiments, a communication apparatus stores therein an operation mode indicating whether the communication apparatus is a publisher or a subscriber, and includes a message processing unit that generates a transmission message and analyzes a reception message and a nonvolatile memory. When the communication apparatus is subscriber, the communication apparatus sends a repair message to request a retransmission of a data chunk not successively received. When the communication apparatus is publisher, the communication apparatus selectively retransmits the data chunk based on the repair message.

A mode of a publisher or a subscriber is stored. Also, a first identifier indicating affiliation to a first group is stored. In a case of the publisher, a transmission message including ToC information, which is a list of the first identifiers and data to be transmitted, is transmitted to an outside. In a case of the subscriber, when a received message includes the first identifier, data included in the message is stored into a non-volatile memory, and when it is determined that all data in the ToC information stored in the received message are already received and that the number of publishers is less than a threshold, the stored mode is changed to the publisher.

According to one embodiment, a storage device management device is connected to a random access memory and a first storage device. When the random access memory includes a free region sufficient to store write data, the write data is stored onto the random access memory. Data on the random access memory selected in the descending order of elapsed time from the last access is sequentially copied onto the first storage device, and a region in the random access memory which has stored the copied data is released. When stored on the random access memory, the read data is read from the random access memory to the processor. When stored on the first storage device, the read data is copied onto the random access memory and read from the random access memory to the processor.

Storage device management device and method for managing storage device

According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets.

Semiconductor device and memory protection method

According to the embodiments, when a communication apparatus is a publisher, a transmission message including a first identifier is transmitted using first transmission power, when the communication apparatus is a subscriber, data of a reception message including the first identifier is stored in a nonvolatile memory, when at least a part of the reception message cannot be received, a repair message for requesting retransmission of the reception message is transmitted from a wireless interface unit using second transmission power, and when there is no response, a repair message is transmitted using third transmission power that is larger than the second transmission power.

A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.

Information processing device including memory management device managing access from processor to memory and memory management method

A digital content protection method includes distributing, together with an encrypted content, an encrypted protected program key, a protected content key, and a protected code including an individual instruction code, at least some elements of which are designed according to a unique operation code specification for each content player or for each content player group.

Protection method, decryption method, player, storage medium, and encryption apparatus of digital content

An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.

Device and memory system for swappable memory

According to one embodiment, a memory management unit which controls a first memory as a nonvolatile memory and a second memory as a volatile memory, the memory management unit includes, judging whether data in the first memory desired to be accessed is stored in the second memory, setting an error flag to issue error data when the data is not stored in the second memory, and reading, into a free space of the second memory, the data to be accessed in the first memory.

Memory management unit and memory management method for controlling a nonvolatile memory and a volatile memory

Device and memory system for memory management using access frequency information

A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.

Resistance change memory device

Growing community of inventors

Yokohama, Japan

Hiroto Nakai