Sumitomo Electric Industries, Limited

Hirotaka Oomori

Takashi Tsuno

Toru Hiyoshi

Shigeo Hayashi

So Tanaka

Ren Kimura

Tatsushi Kaneda

Satoshi Hatsukawa

Mitsuhiko Sakai

Jiro Shinkai

Kenichi Sawada

Masaki Migita

Kenichiro Uchida

Yoshisumi Kawabata

Haruki Yoneda

Shigeru Inano

A semiconductor apparatus includes a heatsink plate, a substrate disposed on the heatsink plate, a circuit pattern disposed on the substrate, a semiconductor chip disposed on the circuit pattern, a case fixed to the heatsink plate and surrounding an outer perimeter of the substrate, a terminal attached to the case, and a wire configured to electrically connect the terminal to the circuit pattern or to the semiconductor chip. In a plan view as viewed in the thickness direction of the heatsink plate, a portion of the circuit pattern overlaps the terminal.

Semiconductor apparatus

A semiconductor device of the present disclosure includes: a semiconductor substrate having a first main surface; a first aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the first aluminum electrode being disposed on the semiconductor substrate; a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; and a copper film. The second surface exposed from the opening is provided with a recess that is depressed toward the first surface. The copper film is disposed in the recess.

Semiconductor device

A semiconductor includes: a substrate; a circuit pattern on the substrate, and including a first region, a second region located away from the first region, and a third region between the first region and the second region; a first chip disposed in the second region and including a diode; a second chip disposed in the third region, the second chip including a vertical transistor having a source pad disposed on a surface opposite to a surface facing the third region in a thickness direction of the substrate, and a gate pad disposed at a position different from the source pad; a first wire including a first bonded portion bonded to the first region, a second bonded portion bonded to the second chip, and a third bonded portion bonded to the first chip; and a second wire arranged to be adjacent to the first wire with the gate pad sandwiched therebetween.

A semiconductor module includes a base member including a circuit board on which a positive electrode pad and a negative electrode pad are provided and on which a semiconductor device is mounted to be electrically coupled to the positive electrode pad and the negative electrode pad, a housing that is attached to the base member so as to surround the positive electrode pad and the negative electrode pad, the housing being formed in a frame shape, a first electrode plate that is electrically coupled to the positive electrode pad, the first electrode plate having a flat plate portion, and a second electrode plate that is electrically coupled to the negative electrode pad, the second electrode plate having a flat plate portion. The flat plate portion of the first electrode plate and the flat plate portion of the second electrode plate are arranged in a parallel-plate configuration within the housing.

Semiconductor module

A semiconductor module includes: a circuit board; a semiconductor chip having a first electrode pad on a first surface, bonded to the circuit board at a second surface that is opposite to the first surface, and having side surfaces intersecting the first surface and the second surface; an external terminal electrically connected to the first electrode pad; and an insulating member configured to fix the external terminal, wherein by the insulating member contacting the side surfaces of the semiconductor chip at a plurality of locations, parallel movement and rotational movement of the semiconductor chip relative to the insulating member in a plane parallel, to the first surface are restricted, and wherein the external terminal penetrates the insulating member.

A semiconductor device includes: a base plate having a first surface and having a first contact area in the first surface; a metal plate having a second surface, disposed such that the second surface faces the first surface, and having a second contact area in the second surface; a bonding material disposed between the first surface and the second surface and in contact with the first contact area and the second contact area to bond the metal plate and the base plate; an insulating plate disposed on the metal plate; a circuit member disposed on the insulating plate; a semiconductor element mounted to the circuit member; and a sealing material that covers the metal plate, the bonding material, the insulating plate, the circuit member, and the semiconductor element to seal a space above the base plate, wherein outside the second contact area, the second surface has a non-contact area that is not in contact with the bonding material, wherein on the base plate, a groove portion facing the non-contact area and surrounding the first contact area is provided, and wherein, in a plan view as viewed in a thickness direction of the base plate, an inner periphery of a corner portion of the groove portion has a first curve.

A semiconductor device includes a base plate; a metal plate above the base plate; a bonding material between the base plate and metal plate, bonding the metal plate to the base plate; an insulating plate on the metal plate; a circuit member on the insulating plate; a semiconductor element mounted on the circuit member; and a sealing material to seal a space on the base plate. The metal plate includes a bottom surface area along a periphery, exposed from the bonding material. The base plate includes a groove-shaped first recess formed along the periphery of the metal plate and faces the bottom surface area. The base plate also includes a groove-shaped second recess that is spaced apart from the first recess and that is formed on the inner side relative to the first recess. The bonding material is disposed in at least a part of the second recess.

A semiconductor moduleaccording to one embodiment includes a first circuit board, circuit units and a first plate member; the circuit units include a second plate member, a vertical type transistor and a second circuit board; n first circuit unit of N circuit units electrically connect a back surface side conductive region to the first input interconnection pattern of the first circuit board; (N&#x2212;n) second circuit unit of the N circuit units electrically connect the third conductive pattern and the fourth conductive pattern of the second circuit board to the first control interconnection pattern and the second input interconnection pattern of the first circuit board; the first plate member electrically connects the fourth conductive pattern of the first circuit units to the second plate member of the second circuit units; and the gate electrode pad of the vertical type transistor contained in the first circuit unit is electrically connected to the first control interconnection pattern of the first circuit board.

A semiconductor apparatus includes a base plate, a metal plate disposed on the base plate, a bonding material disposed between the base plate and the metal plate to be in surface-to-surface contact with the base plate and the metal plate to bond the metal plate to the base plate, an insulating plate disposed on the metal plate, a circuit member disposed on the insulating plate to be in surface-to-surface contact with the insulating plate, a semiconductor device mounted on the circuit member, and an encapsulating material covering the metal plate, the bonding material, the insulating plate, the circuit member, and the semiconductor device to encapsulate an area over the base plate, wherein a bottom face area of the metal plate along the outer perimeter of the metal plate is not covered with the bonding material, wherein the base plate has a groove-shape recess that is disposed along the outer perimeter of the metal plate to face the bottom surface area, wherein the recess has an area having a first depth and a deeper area deeper than the first depth, and the deeper area is disposed beside an inner-side sidewall of the recess, and wherein at least a portion of the deeper area has the bonding material disposed therein.

A semiconductor module according to an embodiment includes a circuit substrate, a first vertical transistor having a first main electrode pad facing and coupled to a first input interconnect pattern of the circuit substrate, and having a first gate electrode pad coupled to a first control interconnect pattern of the circuit substrate, a second vertical transistor having a fourth main electrode pad facing and coupled to a second input interconnect pattern of the circuit substrate, and having a second gate electrode pad facing and coupled to a second control interconnect pattern of the circuit substrate, a surge voltage absorbing device connecting the first and second input interconnect patterns to absorb surge voltage, and a plate member connecting a second main electrode pad of the first vertical transistor and a third main electrode pad of the second vertical transistor.

A semiconductor module according to one embodiment includes a circuit substrate and first and second transistors for upper and lower arms of a power conversion circuit. The circuit substrate includes a substrate having first and second insulating parts and a conductive layer disposed therebetween, first and second input interconnection patterns coupled to the first and second input terminals, and an output interconnection pattern coupled to an output terminal. The first and second transistors are electrically coupled to the first and second input terminals through the first and second input interconnection patterns, respectively. The conductive layer has a first area situated opposite the first input interconnection pattern and a second area electrically coupled to the first area. The second area is electrically coupled to the second input interconnection pattern. The conductive layer is insulated from the first input interconnection pattern and the output interconnection pattern by the second insulating part.

Semiconductor module for a power conversion circuit for reliably reducing a voltage surge

A semiconductor module according to an embodiment includes an insulating substrate having a power conversion circuit mounted thereon, a first transistor constituting an upper arm, a second transistor constituting a lower arm, a first input interconnection pattern coupled to a positive-side input terminal, a second input interconnection pattern coupled to a negative-side input terminal, an output interconnection pattern coupled to an output terminal, and an absorbing device configured to absorb surge voltage, wherein the first input interconnection pattern includes a first-transistor mounting area on which the first transistor is mounted, wherein the output interconnection pattern includes a second-transistor mounting area on which the second transistor is mounted, wherein the second input interconnection pattern includes an absorbing-device connecting area disposed between the first and second transistor mounting areas, and wherein the absorbing-device connecting area is electrically coupled to the first-transistor mounting area through the absorbing device.

An optical transmitting unit comprises an integrated optical transmitter module including an LD, a TEC configured to heat or cool the LD, a thermal sensor configured to sense a temperature of the LD, and a package configured to house the LD, the thermal sensor, and the TEC, an MCU, and a temperature detection circuit configured to detect a temperature outside the package. The thermal sensor is thermally coupled with the TEC and is also thermally coupled with the outside of the package, and the MCU defines data output from the temperature detection circuit as an internal temperature when the LD is being energized, and estimates the data of internal temperature on the basis of the temperature detected with the thermal sensor and the data when the LD is not being energized.

Optical transmitter

An algorithm to reduce a peak current for a transmitter module with multiple laser diodes (LDs) is disclosed. When the current temperature of the LDs is higher than the target temperature, the thermo-electric cooler (TEC) controller is first activated then the LD driver to drive the LDs is subsequently activated with a substantial delay. When the ambient temperature of the LDs is lower than the target temperature, the LD driver is first driven; then, the TEC controller is subsequently activated.

Optical transmitter having multiple optical sources and a method to activate the same

An optical receiver able to distinguish a failure occurred in one of multiplexed signals from a failure in the transmission medium is disclosed. The optical receiver includes an optical de-multiplexer, optical devices, a signal processor, and a controller. Each of the optical devices converts the de-multiplexed signal into an electrical signal. A clock is extracted from one of the electrical signals. The processor decides, based on the electrical signals and the clock, one of the multiplexed signals falls in a failure.

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Yokohama, Japan

Hirotaka Oomori