Mitsubishi Electric Corporation

Renesas Electronics Corporation

Hirotaka Motai

Hitoshi Suzuki

Koji Adachi

Yasuhiro Tawara

Tomohisa Yamaguchi

Akio Idehara

Hiroki Konaka

Shinichi Ochiai

Masahiro Deguchi

Toshiaki Tomisawa

Yurika Terada

Bampei Kaji

Shunsuke Nishio

Yuya Ono

Toshiyuki Otani

A slave node () is slave equipment that operates in accordance with a control frame transmitted from a master node (). The slave node calculates a control frame statistic that is a statistic of one or more control frames transmitted from the master equipment and estimates a master environment value based on the calculated control frame statistic. The slave node measures a slave environment value. The slave node estimates a frequency deviation of a master clock based on the estimated master environment value and estimates a frequency deviation of a slave clock based on the measured slave environment value. The slave node modifies a clock value of the slave clock based on a difference between the frequency deviation of the master clock and the frequency deviation of the slave clock.

Slave equipment, computer readable medium, and embedded system

A process control unit () causes a plurality of control-target processes to operate in a memory area of a size equal to or smaller than a limiting value x. When a stopping process is detected, a resource allocation unit () allocates a size of a usable memory area for each of the control-target processes as a relaxed limiting value. When the stopping process is detected, the process control unit () causes each of the control-target processes to perform fallback operation in a memory area of a size equal to or smaller than the relaxed limiting value allocated to the process by the resource allocation unit ().

Resource control device, resource control method, and computer readable medium

A built-in apparatus includes a response time buffer () that stores a response time, a calculation result buffer () that stores a calculated frame, and a transmission part (). The transmission part () obtains second data and start processing for calculating a frame check sequence from the second data, upon receiving a transmission command (), judges whether frame transmission processing for generating and transmitting the second data and the frame check sequence calculated from the second data as a response frame () will be completed within the response time, and transmits the calculated frame stored in the calculation result buffer () as the response frame () when judging that the frame transmission processing will not be completed within the response time.

Built-in apparatus, communication method, and computer readable medium

A computer system includes a first bus, a second bus, and a third bus, a first bus bridge that is disposed between the first bus and the second bus, and detects a bus error on the second bus, a second bus bridge that is disposed between the second bus and the third bus, and detects a bus error on the third bus, a first device coupled to the second bus, a second device coupled to the third bus, an interrupt controller that notifies a bus error in accordance with the detection of the bus error, and a multi-thread processor. The multi-thread processor includes a schedule register that stores an execution order and data for a plurality of virtual CPUs, and a virtual CPU execution circuit that executes the virtual CPUs in accordance with the execution order.

Computer system

A computer system includes an interrupt controller to notify a bus error occurrence, and a multithreaded processor. The multithreaded processor includes a schedule register that settles a sequence of performing a plurality of virtual CPUs and stores data for virtual CPUs to be performed, and a virtual CPU execution portion that performs virtual CPUs according to a sequence settled by the schedule register. Virtual CPUs operate different operating systems (OS's) and include a first virtual CPU that operates a management OS to manage other OS's. When notified of bus error occurrence, the virtual CPU execution portion operates only the first virtual CPU regardless of an execution sequence settled in the schedule register. The first virtual CPU reinitializes a bus where an error occurred.

An interrupt signal accepting apparatus manages two OSs, relates devices sharing the same interrupt number respectively with an OS caused to perform an interrupt processing and an interrupt priority unique to a device, and manages an interrupt number priority conversion table showing the relation between the interrupt number and the interrupt priority. Each device continuously outputs an interrupt request having the same interrupt number until the interrupt processing is completed. An interrupt controller converts the interrupt number into the interrupt priority in accordance with the interrupt number priority conversion table when there is an interrupt signal from the devices. An interrupt signal control section causes a running OS to perform the interrupt processing to change the interrupt priority in the interrupt number priority conversion table when the converted interrupt priority matches an interrupt priority related to the running OS, and stops the running OS and starts the other OS when the interrupt priorities do not match.

Interrupt signal accepting apparatus and computer apparatus managing operations of at least two operating systems

There is a need to provide a computer system capable of preventing a failure from propagating and recovering from the failure. VCPU#through VCPU#each operate different OS's. VCPU#operates a management OS that manages the other OS's. When notified of bus error occurrence, a virtual CPU execution portionoperates only VCPU#regardless of an execution sequence stored in schedule register A. VCPU#reinitializes a bus where an error occurred.

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Tokyo, Japan

Hirotaka Motai