Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Toray Industries, Inc.

Hirotaka Ito

Yoshihiro Tabira

Hiroshi Yoshida

Isamu Ishimura

Hironori Shinkai

Masanori Sugino

Atsushi Morimoto

Kazuki Hattori

An airbag cushion has a plurality of base fabrics and adhesive joints for bonding each of the plurality of base fabrics, wherein the adhesive joint includes a sealing adhesive, a tensile strength (S1) between the base fabric and the adhesive joint is 500 N/5 cm or more, and an application width (L1) and an application thickness (L2) of the adhesive joint satisfy inequality (1):

Airbag cushion

An external storage device includes a media control section (), a monitoring section (), an interface section () and a power control section (). The media control section () drives a recording media and performs data access to the recording media. The monitoring section () monitors whether the data access by the media control section () can be performed or not. The interface section () performs communication with a host device. When the monitoring section () detects that the data access can not be performed, the power control section () limits power supply to the interface section (). When the monitoring section () detects that the data access can be performed, the power control section () re-starts the power supply.

External storage device and power management method for the same

The multi-initiator control unit for performing packet-unit communication with each of a plurality of devices connected via a transmission line includes: a packet filter for analyzing a received packet and outputting the results; a plurality of command control circuits each for controlling a command processing sequence performed with the corresponding device; a multi-control circuit for giving sequence execution permission to one of the plurality of command control circuits; and a packet processing circuit for generating a packet containing information output by the permission-given command control circuit and outputting the packet for transmission, and also outputting a received packet according to the analysis results output by the packet filter.

Multi-initiator control unit and method

If a packet processing controller at a consumer node has failed to process a received packet within a predetermined amount of time, a packet processing control timer detects a time-out and informs a CPU of that. In response, the CPU issues packet processing suspend instruction and packet transmit instruction for the controller by way of a register. In accordance with these instructions, the controller suspends the current packet processing and produces header and data for a WRS packet, which is transmitted to a producer node through a bus. In this manner, a packet can be processed without causing a time-out at the producer node.

Packet transmission/reception processor

A reception buffer, a transmission buffer, a transmission-reception buffer, a reception filter, a transmission filter and a packet processor are provided. If a response packet paired with a request packet has been received during a data exchange operation, then the reception filter stores the response packet received on the transmission-reception buffer and informs the packet processor of response detected. Alternatively, if a packet that has nothing to do with the current data exchange operation has been received, then the reception filter stores the received packet on the reception buffer and issues a suspension instruction to the packet processor. And when a transaction being carried out at the time of reception is completed, the packet processor suspends the data exchange. In this manner, the overheads involved with firmware processing by a central processing unit can be reduced and data can be exchanged at higher speeds.

Data exchange unit

A write register access circuit comprises data input terminals , 32 pieces of first-stage flip-flops , 16 pieces of second-stage flip-flops connected to the first-stage flip-flops , an OR gate , a flip-flop , a NAND gate , 16 pieces of data selector circuits , 32 pieces of gate circuits , and 32 pieces of data output terminals , and the write register access circuit is connected to a CPU circuit through an interruption request circuit Z. Therefore, when the write register access circuit is included in an LSI, the write register access circuit enables parallel processing between the CPU and the LSI without necessity of matching the instruction word length of the CPU and the bus width of the LSI, providing an internal bus width changing switch, and dealing with the problem at the software end of the CPU. Further, data transfer rate is increased.

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Osaka, Japan

Hirotaka Ito