Hitachi, Ltd.

Hirotaka Hara

Masaru Kokubo

Motohiro Kokumai

Toshiro Suzuki

Tatsuya Kameyama

Tatsuko Shinotsuka

Yukihito Ishihara

Haruo Kamimaki

A filter processing unit 2 receives the output of an oversampling-type analog/digital (A/D) converter circuit 1. Predetermined information is acquired by a compensation circuit 3-1 with predetermined timing from the filter processing unit 2 in the course of processing for producing a filter output for a predetermined integration-phase state and the predetermined information is fed back to the filter processing unit 2 as compensation information representing a difference in magnitude between a filter output with an integration phase lagging behind or leading ahead of the predetermined integration-phase state and a filter output with an unchanged integration phase in order to produce a controllable-phase filter output DMout. The timing for the acquisition of the compensation information by the compensation circuit 3-1 is controlled by a control circuit 7-1.

Running-average/decimation filter for an oversampling A/D converter

An automatic equalizer is capable of updating tap coefficients and constituted to vary the frequency at which to update the tap coefficients depending on the magnitude thereof. There are provided a plurality of ways to vary the frequency at which to update the tap coefficients. One way is to divide the taps into two groups, one group having its tap coefficients updated at a relatively high frequency, the other group having its tap coefficients updated at a relatively low frequency. Another way is to vary the frequency at which to update the tap frequency based on the result of suitably judging the magnitude thereof.

Semiconductor integrated circuit containing an automatic equalizer

A signal processing method and system in a receiving apparatus including a receiving equalizer circuit are provided for extracting transmission data from a received signal inputted via a transmission path every transmission frame having a predetermined synchronization pattern and transmission data. A phase error is detected from the received signal extracted in synchronism with a sampling signal in the receiving equalizer circuit. The frequency of the sampling signal is controlled until the phase error becomes minimum. In parallel, it is detected whether the frame synchronization pattern is present in the received signal in a predetermined interval or not. When the presence of the frame synchronization pattern is not detected after the phase has been stabilized by frequency control of the sampling signal, the sampling phase of the received signal is judged to be in the quasi-convergence state. Then the frequency of the sampling signal is forcibly changed largely. The frequency control of the sampling signal and detection of the frame synchronization pattern are repeated.

Transmission apparatus and method

A method for cancelling an echo in a network termination (NT) of a transmission system and an apparatus therefor are disclosed. The method comprises the steps of detecting an end of transmission of a specific data train in an up-going signal when the phase of the received clock is to be shifted for synchronization during the transmission of the up-going signal from the NT, shifting the phase of the receiving clock when the end of transmission is detected, sampling a residual echo signal of the echo of the specific data train not cancelled by the adaptive filter, determining a correction value for the output of the adaptive filter and storing the correction value and adding a sign corresponding to the direction of the phase shift to the correction value after the phase shift and adding the result to the output of the adaptive filter to cancel the echo of the specific data train.

Growing community of inventors

Kodaira, Japan

Hirotaka Hara