Nissan Motor Company Limited

Hiroshige Ozawa

Takeshi Fujishiro

Shigeo Aono

Mitsuhiko Ezoe

Hiromichi Nakamura

A Karman vortex type flow rate measuring apparatus is provided with a plurality of vortex shedding members each having a different effective width, and a plurality of vortex detecting elements. The distance between the vortex detecting elements is so selected that it coincides with the distance between the vortices of some one of the vortex trains induced by respective vortex shedding members. The apparatus enables a positive and accurate detection of the vortices, and a compensation for drop out of the vortex shedding.

Fluid flow measuring apparatus

First and second transistors are connected in a monostable multivibrator configuration. A capacitor is coupled between the collector of the first transistor and the base of the second transistor. A first control voltage is applied to the collector of the first transistor to charge the capacitor when the second transistor is conductive. A constant current source is provided to charge the capacitor at a constant rate determined by a second control voltage. The stored energy is discharged through the first transistor when energized in a successive cycle. The capacitor is recharged by the constant current source through the first transistor to linearly raise the potential at the base of second transistor. The transistors are triggered by the distributer of an engine so that a control pulse is generated for each revolution of the engine's output shaft. The width of the output pulse from the collector of second transistor is proportional to the first input voltage and inversely proportional to the second input voltage. When the pulse generators are cascaded in a suitable manner, the width of the output pulse is proportional to the product of the two input voltages.

Circuit for generating pulses with duration proportional to quotient of

Circuit testing apparatus includes a pulse oscillator providing clock pulses, a binary counter for counting the clock pulses to successively generate binary numbers, and a translator which translates the successive binary numbers into a series of test patterns. The test patterns include a series of input bit patterns used to energize the input leads of an electronic logic circuit under test and a series of output binary digits, each of which corresponds to the respective one of the input patterns. Each of the binary digits is compared with an output from the logic circuit under test. When the circuit tested is not functioning as prescribed for a particular set of input pattern, a noncoincidence signal will be produced to disable the binary counter in order to permit the test operator to register the test mode in which the trouble occurred. The binary counter may be enabled manually after registration to complete the prescribed number of tests. The presence of a noncoincidence signal is represented by binary digits and stored in a shift register. The stored bits are translated into information indicating the location of a circuit trouble, if any.

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Yokohama, Japan

Hiroshige Ozawa