Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Matsushita Electronics Corporation

Tower Partners Semiconductor Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Tower Semiconductor Ltd.

Matshushita Electric Industrial Co., Ltd.

Hiroshige Hirano

Tatsumi Sumi

Tetsuji Nakakuma

Nobuyuki Moriwaki

Toshiyuki Honda

Koji Takemura

George Nakane

Yutaka Itoh

Koji Koike

Hikari Sano

Kunisato Yamaoka

Masao Takahashi

Yasuo Murakuki

Masahiko Sakagami

Toshio Mukunoki

Yukitoshi Ota

Kouji Asari

Hiroaki Kuriyama

Takashi Miki

Shunichi Iwanari

Yasushi Gohou

Masato Takeo

Takashi Taniguchi

Hisakazu Kotani

Kazuhiro Kaibara

Naomi Miyake

Taichi Nishio

Koji Asari

Yutaka Itou

Yakov Roizin

Yoshihisa Nagano

Takayuki Yamada

Masaya Okada

Erez Sarig

Fumito Itou

Micha Gutman

Kenji Tateiwa

Michinari Tetani

Masakazu Hamada

Shigeo Chaya

Nobuaki Tarumi

Chikako Chida

Atsushi Noma

A semiconductor device includes a memory cell on a semiconductor substrate. The memory cell includes a memory element, a first assistance element, and a second assistance element. The memory element includes a source region and a drain region, and a selection gate and a floating gate in series therebetween. The first assistance element includes a first impurity region and a first gate. The second assistance element includes a second impurity region and a second gate. The first and second gates are electrically connected to the floating gate. The second impurity region is connected to a signal line that is connected to the drain region or a signal line that is connected to the selection gate.

Semiconductor device having a memory element with a source region and drain region and having multiple assistance elements

A semiconductor device includes a storage element write unit including a storage element configured to be electrically written only once and store two values, a write controller connected to the storage element through a first node signal and configured to perform a write to the storage element based on a write control signal instructing a write to the storage element, and a write state detection circuit configured to detect that the storage element is in a write state based on a measurement signal obtained by measuring the first node signal. In a case where the write controller receives a detection signal indicating that the storage element is in the write state from the write state detection circuit after start of a write to the storage element, the write controller stops write operation after a lapse of a predetermined time from detection of the write state of the storage element.

Semiconductor device for writing to a storage element

First and second memory cells are arranged on a semiconductor substrate. The memory cell includes, between a first or second source region and a first or second drain, a configuration in which a first or second selection gate and a first or second floating gate are arranged in series. The first memory cell and the second memory cell are adjacent to each other in a first direction. A first signal line extending in the first direction and connected to the first and second selection gates is further provided. The first and second source regions are configured to share a first region. The first selection gate extends in a direction different from the first direction.

Semiconductor device

An active region includes a body region in which first and second transistors are formed, a connection portion to which a potential of the body region is connected, and a lead portion that connects the body region and the connection portion. Source regions or drain regions of the first and second transistors formed in the body region are provided in a common region. Each of the lead portions extends from a corresponding channel region such that the lead portions are isolated from each other, and a gate electrode extends thereon. A width of the lead portion is narrower than a distance between corresponding ones of contact portions of the source regions and the drain regions of the first and second transistors. A width of the connection portion is equal to or narrower than a gate width of the gate electrode extending on the lead portion.

A semiconductor device includes a memory cell formed on a semiconductor substrate. The memory cell includes a first source region and a first drain region that are formed in the semiconductor substrate and a first selection gate, and a first floating gate disposed in series between the first source region and the first drain region. A first floating gate transistor including the first drain region and the first floating gate has a threshold set lower than a threshold of a first selection gate transistor including the first source region and the first selection gate.

Semiconductor device and method for operating the same

A semiconductor device of the disclosure comprises: a first wiring disposed on a semiconductor substrate; a first insulating film disposed on the first wiring; a first via disposed in the first insulating film so as to be connected to the first wiring; a second wiring disposed on the first insulating film so as to be connected to the first wiring through the first via; a first organic insulating film disposed on the second wiring; a second via disposed in the first organic insulating film so as to be connected to the second wiring; a third wiring disposed on the first organic insulating film so as to be connected to the second wiring through the second via; and a second organic insulating film disposed on the first organic insulating film. A pad opening portion through which the third wiring is exposed is provided in the second organic insulating film, and the first via, the second via, the second wiring, and the third wiring are made of metal whose main component is copper.

A semiconductor device includes a first insulating film, a first wiring, a second insulating film, and a second wiring. The first insulating film is formed on a semiconductor substrate. The first wiring is formed on the first insulating film. The second insulating film is provided on the first insulating film to cover the first wiring. The second wiring is formed on the second insulating film. Furthermore, the second insulating film has a first opening part and a second opening part which expose the first wiring. The second wiring has a seed layer and a first plating layer. The first plating layer covers an entire side surface of the seed layer. The seed layer is not provided in the second opening part and a periphery thereof.

A semiconductor device includes a first wiring layer stacked over element electrodes above a silicon substrate and a second wiring layer stacked over the first wiring layer. The first wiring layer includes first source electrode wires and first drain electrode wires. The second wiring layer includes second source electrode wires and second drain electrode wires. The first wiring layer includes a first region and second regions. In the first region, each of the first source electrode wires and the first drain electrode wires is continuous. In each of the second regions, each of the first source electrode wires and the first drain electrode wires is discontinuous. Second source electrode wires and second drain electrode wires are arranged to alternately over the first regions and the second regions in one direction. External connection terminals are not connected over the second regions, and are connected over the first regions.

A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.

Semiconductor device having seal wiring

A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.

Semiconductor device having a pad and plurality of interconnects

A semiconductor device includes: a first insulating film formed on a substrate; a pad embedded in the first insulating film; and a second insulating film that is formed on the first insulating film and has an opening exposing at least part of the pad. The pad includes a plurality of pad interconnects, and an interconnect link is provided to electrically connect adjacent interconnects among the plurality of pad interconnects. The width of the pad interconnects is smaller than the height of the pad interconnects and larger than the width of the interconnect link.

Semiconductor device having a pad

A semiconductor device includes a first interconnect layer and a second interconnect layer provided above or under the first interconnect layer. The first interconnect layer includes a plurality of first interconnect blocks, and in each of the first interconnect blocks, a first interconnect has a first potential, and extends in at least two or more directions, and a second interconnect has a second potential, and extends in at least two or more directions. The second interconnect layer includes a third interconnect which electrically connects the first interconnect of one of a pair of adjacent first interconnect blocks and the first interconnect of the other of the pair of adjacent first interconnect blocks, and a fourth interconnect which electrically connects the second interconnect of one of the pair of adjacent first interconnect blocks and the second interconnect of the other of the pair of adjacent first interconnect blocks.

A semiconductor device includes an electrode pad formed above a semiconductor substrate, and being a connecting portion for an external electrical connection; a multilayer body including a plurality of first interconnect layers formed in a plurality of insulating films stacked between the semiconductor substrate and the connecting portion and including an upper interconnect connected to the connecting portion, and a via configured to connect the first interconnect layers; a ring body formed in the plurality of insulating films to surround the multilayer body without interposing space, and including a plurality of second interconnect layers and at least one line via linearly connecting the second interconnect layers; and a lead line electrically connecting the connecting portion to an internal circuit. The multilayer body is connected to the ring body by at least one of the plurality of first interconnect layers. The lead line is connected to the ring body.

A semiconductor device includes a lower-layer wire, an upper-layer wire including a wire portion and a first wide portion whose wire width is greater than the wire portion, and a contact formation portion in which a contact portion for connecting the lower-layer wire and the first wide portion with each other is provided. The contact formation portion has a planar shape of which a length Lin a direction parallel to a wire width direction of the first wide portion is greater than a length Lin a direction parallel to a wire length direction of the first wide portion.

A semiconductor device includes a plurality of through vias extending through a substrate. The plurality of through vias are arranged dividedly in three or more via groups. Each of the via groups includes three or more of the through vias that are arranged in two dimensions.

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Nara, Japan

Hiroshige Hirano