Kabushiki Kaisha Toshiba

Hiroshige Fujii

Yukihito Oowaki

Masatoshi Sekine

Kazunori Ohuchi

Hideo Shimizu

Atsushi Masuda

Takehisa Kato

Toshihiko Himeno

Masako Yoshida

Naoki Endo

Fujio Ishihara

Hiroaki Nishi

Ryubi Okuda

Motoki Tokumasu

This invention concerns a semiconductor integrated circuit device comprising a plurality of circuit elements arranged in a chip and operating in response to a same clock signal; clock buffers arranged at intersecting points decided based on positions of the plurality of circuit elements, the intersecting points being included in intersecting points of a pseudo mesh virtually assumed to cover up a region in the chip including the plurality of circuit elements; and a main wiring transmitting the clock signal to the clock buffers.

Semiconductor integrated circuit device having clock buffers and method for arranging the clock buffers on the device

A semiconductor holding device comprises a first transistor circuit including a P type first transistor connected to a first power source, an N type second transistor connected to the first transistor and an N type third transistor connected to the second transistor and a second power source, and a second transistor circuit including a P type fourth transistor connected to the first power source, an N type fifth transistor connected to the fourth transistor and an N type sixth transistor connected between the fifth transistor and the second power source, an input signal being supplied to gates of the P type first transistor and the N type second transistor, a clock signal being supplied to gates of the N type third and sixth transistors, a node of the first and second transistors being connected to gates of the fourth and fifth transistors, and a node of the fourth and fifth transistors serving as an output node.

Semiconductor memory and holding device

An information processing apparatus comprises a first memory, a first cache memory provided for the first memory and having a cache line size according to the bandwidth of the first memory, a second memory having a bandwidth different from that of the first memory, and a second cache memory provided for the second memory and having a cache line size according to the bandwidth of the second memory.

Information processing apparatus

An integrated circuit has configurable logic blocks that are reconfigurable, hard-wired logic blocks that carry out fixed operations, and a memory. The memory stores configuration data for configuring the configurable logic blocks, block-connection data for determining connections between the configurable and hard-wired logic blocks, and partial-circuit-connection data for determining connections between partial circuits each of which consists of logic blocks selected among the configurable and hard-wired logic blocks. These pieces of data are shared by the logic blocks to reduce the number of memories in the integrated circuit and improve the packaging density of the integrated circuit.

Configurable integrated circuit and method of testing the same

A semiconductor integrated circuit for cryptographic process according to the present invention, comprises a randomizing unit for randomizing first input data which is one of two divided parts of input data based on configuration information to identify an algorithm in randomizing process, a function F portion for receiving data which have been subjected to the randomizing process and then applying coding process to the data, and an exclusive logical sum circuit for receiving second input data which is other of two divided parts of the input data and output data from the function F portion and then outputting an exclusive logical sum of the second input data and the output data.

Semiconductor integrated circuit for cryptographic process and encryption algorithm alternating method

Part or all of an instruction decoder is constructed of a first reconfigurable circuit wherein a circuit structure thereof can be changed according to an external signal. Further, a second reconfigurable circuit which is connected to output side of a register file as part of processing unit and wherein a circuit structure thereof can be changed according to an external signal is preliminarily provided. For special use, to achieve a predetermined operating function, the second reconfigurable circuit is reconstructed by the external signal. Further, a particular instruction corresponding to the predetermined operating function is set, and the first reconfigurable circuit is so reconstructed by an external signal that when the particular instruction is inputted, a corresponding control signal is outputted. When the particular instruction is executed, the first reconfigurable circuit outputs a control signal and the second reconfigurable circuit executes the predetermined operating function by that control signal.

Processor and information processing apparatus with a reconfigurable

A reconfigurable circuit is reconstructed to three or more operating circuit blocks. Upon testing, the same data is inputted to each of the reconstructed operating circuit blocks. A majority circuit formed in the reconfigurable circuit compares results of operations of the operating circuit blocks and outputs information indicating which of the operating circuit blocks is in trouble.

Semiconductor integrated circuit and test method therefor

A reconfigurable circuit wherein part or all of an instruction or a result of decoding thereof and output of said register file are inputted and a circuit structure thereof can be changed by an external signal is provided. If a bug occurs when part or all of the instruction or the result of decoding thereof and the output of the register file satisfy a particular condition, the reconfigurable circuit is reconstructed by an external signal so as to output a first signal under that particular condition. An interrupt control circuit controls a processing unit so as to carry out processing based on the first signal or processing to avoid the bug when the first signal is inputted.

Growing community of inventors

Tokyo, Japan

Hiroshige Fujii