Advanced Micro Devices Corporation

Hiroshi Yoshida

Patrick T Chuang

Robert L Yau

Moon-Yee Wang

A content addressable memory system includes a plurality of memory cells arranged in rows and columns in an array of N bit words by M word cells, a plurality of word lines extending through the array for addressing different words in the memory cells, each of the words comprising a plurality of adjacent cells extending in a first direction in the array, a plurality of match lines extending through the array in parallel with the word lines in the first direction, a plurality of bit lines extending through the array in a second direction perpendicular to the first direction, each of the bit lines communicating with the cells in one of the columns extending in the second direction, and a pair of registers connected to the bit lines for performing masking operations on bits in the array.

Content addressable memory array with priority encoder

A content addressable memory array includes an array of M words containing bits configured in N bits for each word. One of the bits in each of the words is a settable skip bit, and during a search of the memory array, the array is examined to detect the presence therein of skip bits. If a skip bit is detected in any one of the words, that word containing the detected skip bit is eliminated from the search. Each word in the array also contains an empty bit which is used to indicate an empty word location in the array. When all empty bits are set, the array is automatically reset to empty or zero.

Content addressable memory array with maskable and resettable bits

A content addressable memory system includes an array of memory cells arranged in rows and columns in an array of N bit cells by M words, with N bits per word, an I/O bus having a bit capacity S which is a submultiple of N, a mode generator for generating a plurality of commands, the commands including a command write command, a data write command, a data read command, and a status read command, the command write and the status read commands being encodable in S bits or less, and multiplexing means for supplying selected ones of the commands to the I/O bus.

Growing community of inventors

Santa Clara, CA, United States of America

Hiroshi Yoshida