Renesas Electronics Corporation

Bridgestone Corporation

Other

Ajinomoto Co., Ltd.

Kabushiki Kaisha Toshiba

Nec Corporation

Ngk Insulators, Inc.

Hitachi Metals, Ltd.

Fujifilm Corporation

Nippon Telegraph and Telephone Corporation

Renesas Technology Corp.

The University of Tokyo

Boehringer Mannheim Gmbh

Tokyo Institute of Technology

Ushio Denki Kabushiki Kaisha

Hiroshi Ueda

Seiji Mochizuki

Toshiyuki Kaya

Katsushige Matsubara

Ryoji Hashimoto

Kenichi Iwata

Keisuke Matsumoto

Tetsuya Shibayama

Ren Imaoka

Naoyuki Goto

Toshio Ishii

Yoshimi Midorikawa

Masahiro Kuroda

Masayuki Gonda

Michio Ishii

Teruyuki Nagamune

Takayuki Koda

Yutaka Wakita

Toyomi Iwata

Shohachiro Nakayama

Hajime Nishimura

Tsunehiro Kawata

Kazuo Suzuki

Hiroshi Yamaguchi

Masakazu Sato

Taneaki Chiba

Tomohiro Une

Kenji Arai

Greg Winter

Paula A Schueler

Shigehito Kishinami

Izumi Kumagai

Kouhei Tsumoto

Takahiko Sugimoto

Hisaaki Yoshigai

Mikio Masunaga

Fumio Bamba

Naomi Ogino

Akiyo Iizuka

Taku Maekawa

Yuki Ohmuro

Walter C Mahoney

Kazuhiro Sato

Tomoaki Nagai

Hiroaki Nakata

Hirohiko Tsuzuki

Akira Sakai

Kaoru Hamada

Makoto Saen

Koji Hosogi

Akio Sekine

Eiji Yamamoto

Koichi Minami

Kazushi Akie

Masakazu Ehama

Yukifumi Kobayashi

Naomi Kobayashi

Fumitaka Izuhara

Kimio Nobeashi

Takafumi Yuasa

Makio Kashino

Nobuhiko Shima

Nobuyuki Yanagi

Minoru Uematsu

Masaki Utsumi

Toshiyuki Yamagami

Eiichi Kato

Kunihiko Toumori

Masaharu Inaba

Yoshiyuki Ohiro

Hiroshi Fukushi

Tomonao Ueda

Norio Shibata

Takashi Oomori

Sumio Miyake

Yujiro Mima

Masataka Okamoto

Tetsuya Kitaguchi

Jiulong Su

Yoshiki Saitou

Masaki Ihara

Chihiro Miyake

Tomoya Tsukahara

Takeshi Sugiyama

Yoshikane Osakabe

Syouji Sawai

Toru Mizuhara

Muneyuki Ozawa

Shirou Okayama

Ryoji Abe

Hiroaki Takagi

A technique for feeding back an image obtained by modulating a motion of a subject in real time is provided. A physical exertion feedback device includes: a modulation unit configured to generate, as a modulated image, an image reflecting modulated motion time-series data, the modulated motion time-series data being obtained by modulating data within a partial time period of input motion time-series data representing a motion of a subject, using reference motion time-series data representing a motion of a teacher, the modulated motion time-series data representing a motion for correcting the motion of the subject; and a presentation unit configured to present the modulated image to the subject, wherein the modulated motion time-series data is, at respective time points from a time point at which the subject starts the motion to a predetermined time point which is hereinafter referred to as a modulation start time point, motion time-series data that matches the input motion time-series data, and is, at respective time points after the modulation start time point, motion time-series data obtained by modulating the input motion time-series data using a predetermined modulation method.

Physical motion feedback apparatus, physical motion feedback method, and program

Provided as a mutant of β glucuronidase suitable for homogeneous immunoassays is a β glucuronidase mutant, wherein, in the amino acid sequence ofβ glucuronidase, methionine at position 516 is substituted with lysine, and tyrosine at position 517 is unsubstituted or substituted with a non-tyrosine aromatic amino acid.

Enzymatic mutant suitable for homogeneous immunoassay method

The purpose of the present invention is to develop a kit capable of detecting antigen or measuring its amount with high sensitivity without requiring an immobilization step and a washing step. The present invention provides a kit for detecting antigen or measuring its amount. The kit comprises a complex of a polypeptide including an antibody light chain variable region and a polypeptide including an antibody heavy chain variable region and a protein M fragment labeled with a fluorescent dye. The protein M fragment is a fragment having a binding ability to the complex.

Kit for detecting antigen or measuring its amount

A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.

Signal processing system, signal processing circuit, and reset control method

Regarding association between an area where compressed data is stored and an area where auxiliary information required to access the compressed data is stored, it is necessary to manage the association by software for each processing unit, so that the processing becomes complicated. A management unit memory area including a compressed data storage area and an auxiliary information storage area including auxiliary information are defined on a memory space. By calculating an auxiliary information address from an address indicating a location on a memory where a management unit memory space is set, an address of the auxiliary information storage area, and an address of the compressed data, the compressed data and the auxiliary information are associated with each other and the auxiliary information is read.

Semiconductor device and memory access method

A video encoding/decoding system includes a video encoding device, and a video decoding device. The video encoding device includes an encoding circuit for encoding an image including a diagnostic image or a normal image. The video decoding device includes a decoding circuit for decoding the image encoded in the encoding circuit, a check signal generation circuit for generating a check signal of the decoded image, a storage circuit for storing the check signal generated by the check signal generation circuit, and a comparison circuit for comparing the check signal stored in the storage circuit with the check signal generated by the check signal generation circuit. The failure is detected by comparing the check signal including an expected value stored in the storage circuit with the check signal including a comparison value generated by the check signal generation circuit by processing the same image data a plurality of times.

Video encoding/decoding system and diagnosis method thereof

A plurality of transfer modules (-to-M) that transfer data between processing units are provided so as to respectively correspond to a plurality of processing units (-to-M). First ring buses (-to-M) connect, for each of the processing units (-to-M), subunits within a corresponding processing unit and the transfer module corresponding to the processing unit so that they form a ring shape. The plurality of transfer modules (-to-M) are connected so that they form a ring shape by a second ring bus ().

Processing apparatus and control method thereof

A display area can be smoothly moved. A semiconductor device sequentially receives a plurality of whole images, each of which includes a plurality of small screen images and which are temporally continuous and form a moving image, and decodes a received whole image. Here, the semiconductor device includes a reception unit that receives the whole image including the small screen images, a determination unit that determines a decoding area which includes a small screen image to be decoded and which is included in the whole image, and a decoding unit that decodes the small screen image in the decoding area which is determined by the determination unit and which is included in the whole image. The determination unit determines a new decoding area when a small screen image of intra frame appears in the decoding area.

Semiconductor device, moving image processing system, method of controlling semiconductor device

A data processing system includes a plurality of data processing devices that perform in parallel data processing on the basis of initial setup data. The data processing devices each has a unique ID and includes a plurality of registers that store the initial setup data and a transfer circuit. The transfer circuit receives packets including a payload that is the initial setup data, shared information, a destination ID and a destination address and, when the shared information indicates that the payload is the initial setup data to be set commonly into the plurality of the data processing devices including its own data processing device, transfers the payload to the register that the destination address indicates irrespective of mismatching between the destination ID and its own ID.

Data processing system

A data processing device includes a data selector circuit that divides a plurality of types of data into another plurality of types of data in accordance with a classification of the data, a plurality of compression circuits that respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data, and a data transmission circuit that transmits the plurality of types of compressed data to a terminal.

Data processing device, data processing system and method

There is a problem that memory protection against access to a shared memory by a sub-arithmetic unit used by a program executed in a main-arithmetic unit cannot be performed in a related-art semiconductor device. According to one embodiment, a semiconductor device includes a sub-arithmetic unit configured to execute a process of a part of a program executed by a main-arithmetic unit, and a shared memory shared by the main-arithmetic unit and the sub-arithmetic unit, in which the sub-arithmetic unit includes a memory protection unit configured to permit or prohibit access to the shared memory based on an access permission range address value provided from the main-arithmetic unit, the access to the shared memory being access that arises from a process executed by the sub-arithmetic unit.

Semiconductor device and its memory access control method

In a picture encoding device and a picture decoding device, the access to a reference frame memory is suppressed. The picture encoding device is comprised of a first encoder for intra picture encoding, a second encoder for inter picture encoding, and an intermediate buffer. A local decoded picture generated by the first encoder is stored as a reference picture in the intermediate buffer, and the inter picture encoding by the second encoder is performed by referring to the local decoded picture in the intermediate buffer. A picture decoding device is comprised of a first decoder for intra picture decoding, a second decoder for inter picture decoding, and an intermediate buffer. A local decoded picture generated by the first decoder is stored as a reference picture in the intermediate buffer, and the inter picture decoding by the second decoder is performed by referring the local decoded picture in the intermediate buffer.

Picture encoding device, picture decoding device, and picture communication system

A video encoding/decoding system includes a video encoding device and a video decoding device. The video encoding device includes an encoding part for encoding a diagnostic image or normal image. The video decoding device includes a decoding part for decoding the image encoded by the encoding part, a check signal generation part for generating a check signal of the decoded image, a storage part for storing the expected value of the check signal of the diagnostic image or the check signal generated by the check signal generation part, and a comparison part for comparing the check signal stored in the storage part with the check signal generated by the check signal generation part, in order to detect failure in all the paths from the image input part of the video encoding device to the image output part of the video decoding device.

A data selector circuit divides a group of data including a plurality of types of data into the plurality of types of data. A first compression circuit and a second compression circuit respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data. The first compression circuit compresses data and obtains compressed data. The second compression circuit compresses data and obtains compressed data. The data transmission circuit-transmits the compressed data and the compressed data to a terminal.

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Tokyo, Japan

Hiroshi Ueda