Hitachi, Ltd.

Hiroshi Uchigaito

Seiji Miura

Kenzo Kurotsuchi

A machine learning system includes a learning section and an operating section including a memory. The operating section holds a required accuracy, and an internal state and a weight value of a learner in the memory and executes calculation processing by using data input to the machine learning system and the weight value held in the memory to update the internal state. An accuracy of the internal state is calculated from a result of the calculation processing and an evaluation value is calculated using the data input to the machine learning system, the weight value, and the updated internal state held in the memory when the calculated accuracy is higher than the required accuracy. The evaluation value is transmitted to the learning section, which updates the weight value by using the evaluation value and notifies the number of times of updating the weight value to the operating section.

Updating weight values in a machine learning system

An image recognition system includes an external information detection unit detecting a distance to a target to be recognized included in an image, a reduced image size determination unit deriving a reduced size of the image based on the distance to the target to be recognized, an image reduction unit reducing the image based on the reduced size of the image, and an image recognition unit including a plurality of recognition process units corresponding to sizes of the images to be recognized and executing the recognition process of the target to be recognized included in the reduced image by means of the recognition process unit corresponding to a size of the image. Instead of the distance to the target to be recognized, a size and a shape of the image, or a clip position of the image from an entire image, may be used.

Image recognition system

An information processing device includes a host and a memory subsystem. The host issues an identifier indicating a data erasable order and a data write command to the memory subsystem and includes an information processing circuit for processing the data. The memory subsystem includes a first memory and a control circuit for writing the data in the first memory. The first memory has a data erase unit size larger than a data write unit size. The control circuit classifies the data based on the identifier, writes the data belonging to a first group in a first simultaneous erase region, in which data can be simultaneously erased, in the first memory, and writes the data belonging to a second group different from the first group in a second simultaneous erase region, in which data can be simultaneously erased, in the first memory. Consequently, the performance and the life of a storage device can be improved, and costs of the storage device can be reduced.

Information processing device

A semiconductor device including a nonvolatile memory cell realizes enhancement of reliability and convenience. The semiconductor device includes a nonvolatile memory unit that includes plural overwritable memory cells (CL), and a control circuit that controls access to the nonvolatile memory unit. The control circuit allocates one physical address to a chain memory array CY in the nonvolatile memory unit, for example. The control circuit performs writing to a memory cell (for example, CL) that is apart of the chain memory array CY according to a first write command with respect to the physical address, and performs writing to a memory cell (for example, CL) that is another part thereof according to a second write command with respect to the physical address.

Semiconductor device

An information processor includes an information processing sub-system having information processing circuits and a memory sub-system performing data communication with the information processing sub-systems, wherein the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a memory controller for controlling data transfer among the first memory, the second memory and the third memory; graph data is stored in the third memory; the memory controller analyzes data blocks serving as part of the graph data, and performs preloading operation repeatedly to transfer the data blocks to be required next for the execution of the processing from the third memory to the first memory or the second memory on the basis of the result of the analysis.

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Tokyo, Japan

Hiroshi Uchigaito