Adv Antest Corporation

Hiroshi Tsukahara

Naoyoshi Watanabe

Katsumi Ochiai

Yokichi Hayashi

Masuhiro Yamada

Toshiyuki Okayasu

Masatoshi Sato

Toshiyuki Negishi

Kazuhiro Yamashita

Mashuhiro Yamada

The delay signal generating apparatus according to the present invention for outputting a delay signal obtained by delaying a reference signal includes: a phase shift device capable of outputting a plurality of shift signals having phases shifted from a phase of the reference signal by different shift amounts, respectively; and a shift signal selector capable of selecting one of the shift signals that has a phase shifted by a predetermined shift amount and outputting the selected shift signal.

Delay signal generating apparatus and semiconductor test apparatus

A fine variable delay circuit includes a buffer having an input connected to a signal input terminal and an output. The buffer has an output impedance and outputs a logical level from the output. The fine variable delay circuit also includes a schmidt trigger buffer having an input connected to the output of the buffer and an output connected to a signal output terminal, a CMOS transistor having a gate and two electrodes, the gate being connected to a connection point between said buffer and said schmidt trigger buffer. In addition, the fine variable delay circuit includes a first switching element connected between one of the electrodes of the CMOS transistor and one terminal of a power supply, a second switching element connected between another of the electrodes of the CMOS transistor and another terminal of the power supply, and a delay setting circuit responsive to a select signal for controlling the first switching element and the second switching element to set simultaneously each of the first switching element and the second switching element to one of an ON and an OFF state, thereby setting a delay.

Variable delay circuit

First and second exclusive-OR gates (hereinafter referred to as EXOR gates) are provided, which are both connected at one input side to a delay input terminal. The other input side of the first EXOR gate is grounded and the other input side of the second EXOR gate is connected to a select signal input terminal. A capacitor is connected between the output side of the first EXOR gate and the output side of the second EXOR gate. The output side of the first EXOR gate is connected to a delay output terminal by way of a buffer which outputs logical levels. The buffer has a threshold value and outputs one or the other binary logical level depending on whether the input thereto is above or below a threshold value.

A waveform formatter for use in testing a semiconductor device is capable of reducing a total size of circuit configuration. The waveform formatter includes a plurality of clock generators in which at low-speed operation, clocks are used to generate waveforms and control signals of drivers, while at high-speed operation, all clocks are used to generate waveforms for drivers. The waveform formatter further includes a parallel-serial converter for converting parallel signals to a serial signal, a data selector for selecting the parallel signals or the serial signal, and a waveform combining circuit for accepting output signals of the clock generators through a format control unit and for generating waveforms and control signals for the drivers using the clocks from the clock generators.

Waveform formatter

The gate of a CMOS transistor formed by a series connection of p-channel and n-channel FETs 21 and 22 is connected to an input terminal 23, and the drain of the CMOS transistor is connected to an output terminal 24. The source of the FET 21 is connected to a positive power supply terminal 20 via parallel-connected switchable resistance elements 37.sub.0, 37.sub.1, 37.sub.2, . . formed by p-channel FETs and having resistance values R.sub.0, R.sub.1, R.sub.2, . . . , respectively. The source of the other FET 22 is connected to a negative power supply terminal 30 via parallel-connected switchable resistance elements 38.sub.0, 38.sub.1, 38.sub.2, . . . formed by n-channel FETs and having resistance values R.sub.0, R.sub.1, R.sub.2, . . . , respectively. Delay setting signals S.sub.0, S.sub.1, . . . are decoded by a decoder 39 and one of more of its output terminals Y.sub.0, Y.sub.1 , . . . go to the high level. The output terminals Y.sub.0, Y.sub.1, Y.sub.2, . . . are connected directly to the gates of the FETs forming the resistance elements 38.sub.0, 38.sub.1, 38.sub.2, . . . , respectively, and are connected to the gates of the FETs of the resistance elements 37.sub.0, 37.sub.1, 37.sub.2, . . . via inverters. The time constant of the charge and discharge for a load capacitance at the output terminal 24 differs with combinations of two resistance elements which are simultaneously turned ON, changing a delay of the input signal accordingly.

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Gyoda, Japan

Hiroshi Tsukahara