Nec Corporation

Renesas Electronics Corporation

Lapis Semiconductor Co., Ltd.

Lapis Technology Co., Ltd.

Nec Electronics Corporation

Getner Foundation LLC

Nlt Technologies, Ltd.

Gold Charm Limited

Hiroshi Tsuchi

Manabu Nishimizu

Masao Iriguchi

Junichiro Ishii

Takashi Nose

Koji Higuchi

Junichirou Ishii

Yoshihiko Nakahira

Hirobumi Furihata

Toshio Watanabe

Yoshihiko Hori

Hiroshi Hayama

Kenji Sera

Kohei Okamoto

Hayato Koizumi

Katsunori Ito

Yuushi Syutou

Yoshikazu Seko

Seiichi Suzuki

Hidenori Ikeno

Kouichi Nishimura

Takashi Ohno

Naoyasu Ikeda

Osamu Ishibashi

Daigo Miyasaka

Kenichi Shiibayashi

Noboru Okuzono

Keigo Otani

Takeshi Nosaka

Nobuyasu Doi

Naoki Taniguchi

Atsushi Hirama

Takuro Kotaki

Sensuke Kimura

Jun-ichirou Ishii

Yoshinori Uchiyama

An output buffer circuit includes: a first transistor supplying a first power supply voltage to a first node upon turning on in response to an input signal; a second transistor supplying a second power supply voltage to a second node upon turning on in response to the input signal; a third transistor connecting between the first and second nodes upon turning on in response to a reverse phase signal of a signal on the first node; a fourth transistor connecting between the first and second nodes upon turning on in response to a reverse phase signal of a signal on the second node; a fifth transistor supplying the first power supply voltage upon turning on in response to the signal on the first node; and a sixth transistor supplying the second power supply voltage upon turning on in response to the signal on the second node.

Output buffer circuit, charge pump device, display drive device, and display device

The disclosure includes: a bias circuit generating first and second bias voltages; a first conductivity type first transistor supplying a first power source voltage to a first node according to the input signal; a second conductivity type second transistor supplying a second power source voltage to a second node according to the input signal; a second conductivity type third transistor receiving the first bias voltage by gate, with source and drain connected to the second and first nodes; a first conductivity type fourth transistor receiving the second bias voltage by gate, with source and drain connected to the first and second nodes; a first conductivity type fifth transistor supplying the first power source voltage to an output terminal according to voltage at the first node; and a second conductivity type sixth transistor supplying the second power source voltage to the output terminal according to voltage at the second node.

Output buffer circuit and semiconductor device

The differential amplifier circuit includes: first conductivity type first to Ndifferential stages each causing a current corresponding to the first or second voltage received at the non-inverting input terminal to flow to a first node and a current corresponding to the output voltage signal received at the inverting input terminal to a second node; a second conductivity type differential stage receiving one of the first and second voltages at the non-inverting input terminal and receiving the output voltage signal at the inverting input terminal, and being activated when the digital data value is within a predetermined range to cause a current corresponding to the one voltage to flow to a third node and a current corresponding to the output voltage signal to a fourth node; and an output amplification stage generating the output voltage signal based on the currents respectively flowing to the first to fourth nodes.

Digital-to-analog converter, data driver, and display device

The disclosure includes a differential amplifier and a first decoder that distributes and supplies a first or a second voltage to each of a plurality of input terminals based on digital data. The differential amplifier includes a Kth-power of 2 pieces of differential pairs each driven by an individually received tail current, and a tail current control circuit that individually supplies the tail current to the Kth-power of 2 pieces of the differential pairs. The tail current control circuit sets a current ratio of the tail current flowing through of two respective differential pairs among the Kth-power of 2 pieces of the differential pairs to be larger than a current ratio of the tail current flowing through other respective differential pairs excluding the two differential pairs.

The disclosure includes: a first transistor, supplying a first power voltage to the output terminal when becoming ON according to a voltage of the input signal received by a gate; a second transistor, supplying a second power voltage to the output terminal in a case of becoming ON in accordance with the voltage of the input signal received by a gate; and an output control part, transitioning to ON by changing a voltage of the gate of the transistor in OFF between the first and second transistors at a change speed based on a current value of a bias current generated by a bias part when the voltage of the input signal changes. According to a voltage change of the input signal, the bias part sets a bias current value to a first value throughout a predetermined period, and switches to a second, lower value in other periods.

Output buffer circuit, data driver, display device, and semiconductor device

A digital-to-analog converter for effectively performing offset cancellation driving to reduce output variations includes: a decoder receiving a K-bit digital data signal and first and second voltages and generating 2voltages each indicating the first or second voltage according to the digital data signal; and a differential amplifier outputting an output voltage having one of 2voltage levels obtained by dividing the voltage between the first and second voltages into 2voltage levels. The differential amplifier includes a MUX receiving 2voltages, 2differential pairs, and an amplification stage to which outputs of the 2differential pairs are supplied. The MUX performs voltage supply to input terminals of each differential pair to actively cause that, in each differential pair, the input voltage to one input terminal in a first state differs from the input voltage to the other input terminal in a subsequent second state.

The disclosure includes: a decoder generating multiple input voltages each having one or the other of two reference voltages selected from multiple reference voltages, using a high voltage digital data signal obtained by increasing the amplitude of a low voltage digital data signal; and a differential amplifier including multiple differential pairs and receiving the input voltages at the non-inverting input terminals of the differential pairs and receiving an output voltage signal at the inverting input terminals to generate an output voltage signal having one of the voltage levels obtained by dividing the two reference voltages into a power of 2. The differential amplifier includes: multiple current sources generating tail currents flowing through the tails of the differential pairs; and multiple clamp transistors provided respectively between the tails of the differential pairs and the current sources and holding a voltage applied to each current source at or below a low voltage.

An output buffer circuit includes a first transistor supplying a first high-voltage power supply voltage in a case of being ON in response to a voltage of an input signal received through a gate; a second transistor supplying a second high-voltage power supply voltage in the case of being ON in response to a voltage of the input signal received through a gate; an output control part that shifts a transistor, of the first and second transistors, being ON to OFF at a time of voltage change of the input signal by changing the voltage in the gate thereof, and turns a transistor being OFF to ON by changing the voltage in the gate thereof at a rate of change based on a current value controlled by a bias voltage, and a bias modulation part that sets a voltage value of the bias voltage to a designated voltage value.

Output buffer circuit, display driver, data driver, and display device

The disclosure includes: first level shift part generating a voltage signal by converting an input voltage signal into amplitude between first negative and positive polarity power supply voltages; second level shift part generating a first polarity voltage signal by converting the voltage signal into amplitude between a reference and the first positive polarity power supply voltage; third level shift part outputting a first-polarity high voltage signal by converting the first polarity voltage signal into amplitude between a higher second positive polarity power supply voltage and the reference; fourth level shift part generating a second polarity voltage signal by converting the voltage signal into amplitude between the reference and the first negative polarity power supply voltage; and fifth level shift part outputting a second-polarity high voltage signal by converting the second polarity voltage signal into amplitude between a lower second negative polarity power supply voltage and the reference.

Signal level shift conversion circuit for display driver and display device converting input voltage signal at synchronized timing

In a first output mode, a signal in which a data pulse having a positive polarity voltage value appears in a predetermined cycle is output as a positive polarity gradation data signal, and a signal in which a data pulse having a negative polarity voltage value appears in the predetermined cycle with a phase different from the positive polarity gradation data signal is output as a negative polarity gradation data signal. In a second output mode, the above positive polarity gradation data signal is generated, and a signal in which a data pulse having a negative polarity voltage value appears in the predetermined cycle with the same phase as the positive polarity gradation data signal is output as the negative polarity gradation data signal. The first and second output modes are alternatively executed, and the output mode is switched within a predetermined period at intervals of the predetermined period.

Display apparatus and data driver

The disclosure provides an output circuit, a display driver including the output circuit and a display device. The disclosure includes a PMOS transistor switch that outputs a positive voltage signal from an output terminal when it is turned on, an NMOS transistor switch that outputs a negative voltage signal from the output terminal when it is turned on, and a voltage control circuit that supplies a voltage obtained by shifting the level of a voltage of a source or a drain when the PMOS transistor switch is turned on to a high potential side to a back gate of the PMOS transistor switch and supplies a voltage obtained by shifting the level of a voltage of a source or a drain when the NMOS transistor switch is turned on to a low potential side to a back gate of the NMOS transistor switch.

Output circuit for liquid crystal display driver providing high reliability and reduced area selectively outputting positive and negative voltage signals

Provided is an output amplifier having: a push-pull output-stage formed by first and second output-stage transistors; and a detection circuit detecting an abnormal output current output by the output amplifier and including: a coupling circuit, generating first and second currents mirroring current flowing in the first output-stage transistor and third and fourth currents mirroring current flowing in the second output-stage transistor, coupling the first and third currents at a first output node, outputting a first voltage at the first output node, coupling the second and fourth currents at a second output node, and outputting a second voltage at the second output node; and a determination circuit, outputting a determination signal indicating normality of an output current based on the first and second voltages. The coupling circuit generates the first to fourth currents. In the reference state, the third current >the first current, the second current >the fourth current.

Load driving circuit, display driver, display apparatus and semiconductor device

The disclosure includes multiple data drivers provided for each predetermined number of data lines. Each data driver receives an image signal; generates, based on the image signal, a positive gradation data signal and a negative gradation data signal; outputs one of the positive and negative gradation data signals to one of a first and second data line groups of a display panel; and outputs the other of the positive and negative gradation data signals to the other of the first and second data line groups. The data driver shifts a phase of the negative gradation data signal in a direction delayed with respect to the positive gradation data signal, and controls a slew rate of an output amplifier for outputting the positive gradation data signal to be lower than that of an output amplifier for outputting the negative gradation data signal.

Display device and data driver

The present invention includes first to j-th DA conversion circuits that are fixedly coupled to one of a plurality of gradation reference voltage generating circuits steadily generating respective gradation reference voltage groups according to gamma correction characteristics of color components different from one another, and select a gradation reference voltage corresponding to a pixel data piece among the gradation reference voltage group generated by the one of gradation reference voltage generating circuits to output the gradation reference voltage as a gradation voltage, an output unit that assigns the first to j-th gradation voltages to respective first to j-th driving voltage signals in a mode according to an output switching signal, and outputs the first to j-th driving voltage signals to the display panel, and an output control unit that generates the output switching signal to switch modes of assigning the first to j-th gradation voltages to the first to j-th driving voltage signals at every division period obtained by dividing a horizontal scanning period by a division number indicated by a division number setting signal, and outputs an input switching signal that causes the first to j-th driving voltage signals to be input in turn to the respective data lines as many as the division number at a cycle of the division periods for the respective first to j-th driving voltage signals.

Display driver and display apparatus

An output circuit includes a first switch that outputs a positive voltage signal received via a first node when in an ON state, a second switch that outputs a negative voltage signal received via a second node when in an ON state, third and fourth switches that set the first and second nodes to a reference power supply voltage when in an ON state, a first voltage follower circuit that supplies a voltage obtained by shifting a voltage of the positive voltage signal supplied to the first node to a negative side by a predetermined voltage difference to a gate of the first switch, and a second voltage follower circuit that supplies a voltage obtained by shifting a voltage of the negative voltage signal supplied to the second node to a positive side by a predetermined voltage difference to a gate of the second switch.

Growing community of inventors

Tokyo, Japan

Hiroshi Tsuchi