Fujitsu Corporation

Hiroshi Tomonaga

Naoki Matsuoka

Kenichi Kawarai

Tsuguo Kato

Satoshi Kuroyanagi

Ryuichi Takechi

Akihiro Hata

Masakatsu Nagata

Satoshi Kakuma

Kazuto Nishimura

Masami Murayama

Takeshi Kawasaki

Tetsuo Tachibana

Masaaki Kawai

Jyoei Kamoi

Kazuo Hajikano

Toshio Shimoe

Satoshi Nemoto

Tadahiro Takase

Teruaki Hagihara

Shiro Uriu

Takashi Kuwabara

Kenichi Okabe

Tetsuaki Wakabayashi

Hidenori Sugai

Jun Tanaka

Toru Katagiri

Naotoshi Watanabe

Yuji Tochio

Atsushi Kitada

Masafumi Katoh

Yasuhiro Ooba

Hideo Abe

Masaki Hirota

Yutaka Ezaki

Katsumi Imamura

Hichiro Hayami

Tsutomu Noguchi

Masamichi Kasa

Hidenao Nakajima

Hiroshi Kurosaki

Yoshimi Watanabe

Shigeyuki Kobayashi

Akira Hakata

Naoki Matuoka

Miwako Watanabe

A communication apparatus includes a receiver configured to receive a signal from a first line, a signal processing circuit configured to perform descrambling processing on the received signal, detect a control signal from the descrambled signal, generate a signal in which an idle signal in accordance with a difference amount between a communication capacity of a second line as a transmission destination and a communication capacity of the first line is inserted in a position where the control signal is detected, and perform scrambling processing on the generated signal, and a transmitter configured to output the scrambled signal to the second line.

Communication apparatus and signal relay method

A packet exchanging device includes queues each configured to accumulate one or more packets, a scheduler unit configured to give a certain permissible reading amount indicating amounts of data of readable packets to each of the queues, and a reading processing unit configured to read the one or more packets from the queues by the permissible reading amount in an order in which a reading condition regarding the permissible reading amount for each queue and an amount of data in the one or more packets accumulated in each queue is satisfied.

Packet exchanging device, transmission apparatus, and packet scheduling method

A packet buffering device includes: a queue for temporarily holding an arriving packet; a residence time predicting unit which predicts a length of time during which the arriving packet will reside in the queue; and a packet discarding unit which discards the arriving packet when the length of time predicted by the residence time predicting unit exceeds a first reference value.

Packet buffering device and packet discarding method

In a packet relay method and device which can reduce a congestion of switching even when segment data are concentrated, segment data dividing portions respectively extract a destination address and a packet length from received packets, divide the packets into predetermined length data based on each packet length, and generates location information indicating locations in the packets respectively for the data. The segment data dividing portions add segment headers in which the location information, the destination address, and an address of its own device as a source address are set are added to each of the data, generate segment data, and provide the segment data to switches within a switch card in parallel.

Packet relay method and device

A signal processing circuit for controlling reading of segment data from a buffer in which a plurality of segment data generated by dividing a frame and received via a plurality of switches which direct each of the segment data to a designated destination are stored, comprises: a start detecting unit which detects a starting segment representing the first transmitted segment data to the switch among the segment data received after the buffer has emptied; a transmission time acquiring unit which acquires a transmission time at which the starting segment was transmitted to the switch; and a read timing control unit which determines, based on the transmission time, a read timing for reading the segment data from the buffer.

Signal processing circuit, interface unit, frame transmission apparatus, and segment data reading method

An apparatus for controlling buffering of an arrival packet. The apparatus includes a packet buffer for temporarily storing each of one or more packets to be transmitted in association with an arrival time thereof, and a packet discard section for determining an arrival packet to be discarded or to be stored in the packet buffer, based on a discard condition defined by using a packet residence time that is calculated on the basis of one or more residence times of one or more packets staying in the packet buffer, wherein the arrival packet is defined as a packet that has newly arrived at the apparatus.

Apparatus and method for controlling buffering of an arrival packet

In a data transmission device and method provided with duplexed switches outputting frames in the order of input for continuing the communication without instantaneous interruptions even though one of the switches is faulted, input interfaces generate frames in which every time data is inputted, input order information indicating the input order is added to the data together with unique information of each input interface and providing the frame generated to the switches in parallel. At least one output interface sequentially stores the frames outputted from the switches for every unique information and selects a first arrived frame among the frames stored with same input order information.

Data transmission device

The packet forwarding apparatus of the present invention includes a packet buffer for temporarily storing packets to be forwarded, a timer for measuring the time of every predetermined unit period, a plurality of first queues corresponding to each of a plurality of address groups that form the packet buffer, a plurality of second queues that are provided corresponding to the property of the packets, a first controller for executing the writing of the packets, and a second controller for executing the discarding of the packets. According to this invention, through managing the first queues and the second queues, packets in the packet buffer can be discarded without the packets being read from the packet buffer.

Packet forwarding apparatus and method for discarding packets

An apparatus includes an input part, a plurality of output parts, and a switching part. The input part inputs a packet and builds at least one forwarding data block including a predetermined destination identifier and packet data extracted from the inputted packet. The switching part includes a forwarding destination storing section for storing, in association with a predetermined destination identifier, a forwarding destination identifier identifying one of the plurality of output parts, and receives the at least one forwarding data block from the input part, and forwards it to one of the plurality of output parts on the basis of forwarding destination storing section which is updated in response to a change in the operating state of the plurality of output parts.

Apparatus and method for forwarding packet data

A memory control device that can improve the speed of a memory interface. A packet disassembly section disassembles packet data into segments and detects packet quality information. A memory management section has an address management table and manages a state in which the packet data is stored according to the packet quality information. A segment/request information disassembler disassembles the segments into data by an access unit by which memories can be written/read, and generates write requests and read requests according to the access unit. A memory access controller avoids a bank access to which is prohibited because of a bank constraint, extracts a write request or a read request corresponding to an accessible bank from the write requests or the read requests generated, and gains write/read access to the memories.

Memory control device

An input line interface device that is used to accommodate packets from a high-speed line efficiently and to reduce a processing load on a back stage caused by routing control. A packet allotting section divides a variable-length packet, allots divided packets to parallel lines, and outputs the packets. A flow group classifying section classifies the packets into flow groups on each of the parallel lines. A sequence number giving section gives the packets sequence numbers corresponding to or independent of the flow groups. A buffering section stores the packets to which the sequence numbers have been given in a buffer or reads out them from the buffer to exercise sequence control over the packets in the flow groups. A flow separating switch separates the packets according to the flow groups and outputs the packets.

Input line interface device and packet communication device

Packets input from input HWs #to #to a packet switch device are buried in time slots A through D. The packet switch device alternately switches the input packets in units of time slots, and inputs the packets to two 4&#xd7;4 switches. The 4&#xd7;4 switches make normal switching, and distribute the packets to respective output ports. Then, the packets output from the two 4&#xd7;4 switches after being switched are alternately multiplexed, and output to output HWs #through #. By making switching in units of packets as described above, a process overhead is prevented from being increased, and also expansion can be easily made. Besides, hardware scale can be made small.

Packet switch device

The packet switch performs a scheduling process by selecting a unicast packet or a multicast packet to be output from each of N input buffers such that input lines and output lines cannot conflict each other for a unicast packet, and such that the input lines cannot conflict each other for the multicast packet.

Packet switch

A scheduling system is capable of causing no deterioration of characteristics even under equal and unequal loads, eliminating the necessity for high-speed repetitive scheduling and complicated arithmetic processes, simplifying its architecture and having its processing speed which does not depend upon a device capability. For attaining this system, an inter-highway pointer is updated to an adjacent line (rightward) when the scheduling for all the lines are finished. If the inter-highway pointer is updated N-times in the same direction (clockwise), the same pointer is updated to an adjacent line in a reverse direction (counterclockwise) in next N-processes of scheduling.

Scheduling control system and switch

A packet switch which can cyclically use &#x3b1; scheduling process results to determine one of M output lines as a destination of a packet stored in each of N input buffer sections by &#x3b1; scheduler sections independently performing scheduling processes is disclosed.

Growing community of inventors

Kawasaki, Japan

Hiroshi Tomonaga