Kabushiki Kaisha Toshiba

Hiroshi Tazawa

Chiaki Takubo

Eiichi Hosomi

Koji Shibasaki

Yoshiharu Tsuboi

Yoichi Hiruta

Naohiko Hirano

Kazuhide Doi

Mamoru Sasaki

Takashi Okada

Takashi Arai

Masao Mochizuki

Ryouichi Miyamoto

A first insulating film is formed on an integrated circuit chip on which an I/O pad is formed. A first opening portion is formed above the I/O pad. A conductive layer and a barrier metal layer which are electrically connected to the I/O pad through the first opening portion are stacked on the first insulating film. The conductive layer and the barrier metal layer are patterned by a single mask. A second insulating film is formed on the resultant structure. A second opening portion is formed in the second insulating film at a position different from that of the first opening portion. A solder bump or metal pad is formed on the barrier metal layer in the second opening portion. The position of the solder bump or metal pad is defined by the second opening portion.

Flip-chip connection type semiconductor integrated circuit device

Disclosed is an apparatus and method for inspecting a connection state of a lead electrode to a bump after TAB (tape automated bonding). An LSI chip is immobilized on a stage. A flexible lead is held by a holding portion and connected to a bump. Above the chip, a CCD camera is provided. The stage is controlled to move up and down by a moving control mechanism. Each of the lead/bump connection states immediately after ILB (Inner lead bonding) is taken in the form of image data and defined as a first image data. A second image data of the lead/bump connection state is taken after the bump and lead are moved to different positions by moving the stage in order to change the position of the chip by means of the moving control mechanism. Whether or not the lead is duly connected to the bump is determined by the comparison of the first and second image data.

Apparatus and method for inspecting an LSI device in an assembling

A semiconductor device comprises a semiconductor chip, an Au bump formed on the semiconductor chip, and Cu lead bonded to the Au bump through a bonding part. The Cu lead has a Cu core and a plated Sn layer formed on the Cu core, and the bonding part is formed of an Au-rich Au--Cu--Sn alloy of a ternary system having a single-phase structure containing 15 at. % or less Sn and 25 at. % or less Cu.

Semiconductor device using gold bumps and copper leads as bonding

The present invention is characterized by providing leads not contributing to actual connection outside the corner leads to prevent the deformation of the corner leads and improve the yield of tape carriers. A device hole is made in a near-central place of an insulating resin film. Around the device hole, outer-lead holes are made. On the insulating resin film, a plurality of wiring patterns are provided and forced to project into the device hole. The plurality of wiring patterns are formed into a plurality of inner leads, of which the outermost ones are determined to be corner leads. On each corner of the device hole, an aligning mark is provided. Dummy leads are provided closer to the aligning marks. The dummy leads are made shorter than the inner leads and corner leads.

Tape carrier and assembly structure thereof

In a flip chip mounting type semiconductor device, on a corner portion of a chip subjected to flip chip mounting, a gate region for injecting a sealing member filled between a mounted board and the chip is arranged. In this semiconductor device, a semiconductor element has a plurality of bumps formed on the peripheral portion on a major surface along each side, a plurality of pad electrodes are formed on the major surface of the circuit board, and the pad electrodes join the bumps. A resin sealing member is filled between the semiconductor element and the circuit board. A gate region through which the resin sealing member is injected is formed on a corner portion of the semiconductor element. In the gate region, no bump is formed, or bumps are arranged at intervals smaller than that in another region. For this reason, the resin uniformly enters the space between the semiconductor element and the circuit board through the gate region.

Flip chip mounting type semiconductor device

A semiconductor device having bump electrodes, each having a structure wherein an alloy layer such as Au--Sn formed by the reaction between the Sn-plated layer on the surface of the inner lead and the bump electrode never reach the bottom surface of the passivation opening portion, is provided. The center of the passivation opening portion is displaced apart from the center of an electrode pad to a direction toward the center of the semiconductor substrate. The center of the passivation opening portion is displaced away from the outer lead and close to the tip end of the inner lead in contrast to the center of the bump electrode. By positioning the passivation opening portion such that the center thereof is located nearer to the center of semiconductor substrate than a center of the bump electrode, without changing the height of the bump electrode or the size of the passivation opening portion, the Au--Sn alloy etc. caused by the reaction between the Sn-plated layer of the inner lead and the metal layer of the bump electrode can be prevented from reaching the passivation opening portion.

Semiconductor device having a bump electrode connected to an inner lead

A semiconductor device comprises a semiconductor chip, an Au bump formed on the semiconductor chip, and Cu lead bonded to the Au bump through a bonding part. The Cu lead has a Cu core and a plated Sn layer formed on the Cu core, and the bonding part is formed of an Au--rich Au--Cu--Sn alloy of a ternary system having a single-phase structure with a composition of 15 atomic % Sn or less and 25 atomic % Cu or less.

Semiconductor device, method of fabricating the same and copper leads

A semiconductor device having a bump electrode includes a first conductive layer formed on a predetermined portion of a substrate. An insulating layer is formed on the substrate and the first conductive layer. The insulating layer has an opening portion such that a predetermined portion of the first conductive layer is exposed. A second conductive layer is formed on the first conductive layer, a side wall of the opening portion of the insulating layer, and an upper surface of the insulating layer. A third conductive layer is formed to cover at least the insulating layer on the first conductive layer and the second conductive layer along the portion. A fourth conductive layer is formed on the third conductive layer to have an over hang portion. A side etch portion is formed surrounded with an over hang portion of the fourth conductive layer, the third conductive layer, and the insulating layer.

Semiconductor device comprising fine bump electrode having small side

In this invention, a designed value of a lead width is previously input and a bonding load suitable for the designed lead width is previously input before the step of continuously bonding a TAB tape on a semiconductor chip is effected. Next, the TAB tape and chip are carried to preset positions, and after recognition of the positions of the tape and chip and the alignment of the tape and chip by use of a CCD camera are completed, the inner lead width is actually measured by use of the CCD camera. The measured lead width is compared with the designed lead width, and when a difference therebetween exceeds a preset reference value, the bonding load is changed to a bonding load suitable for the measured lead width of the lead to be actually bonded based on the ratio of the measured lead width to the designed lead width and then the bonding operation is effected by the suitable bonding load.

Method and apparatus for controlling bonding load of fine lead electrode

A semiconductor assembly comprises first and second containers which contain respective semiconductor chips and are stacked one over another. First and second external leads extending from the insides of the respective containers to outside thereof are bent so as to be connected to each other. The first and the second containers may be provided at corresponding positions with a recess and a projection to be engaged each other for positional alignment. There may be provided first and second heat radiating plates extending from the insides of the respective containers to outside thereof are bent so as to be connected to each other.

Semiconductor assembly having laminated semiconductor devices

A semiconductor device, which uses a film carrier, comprises a semiconductor element with a plurality of terminals, a resin film with a first surface and a second surface, the film having a hole in which the semiconductor element is mounted, and a plurality of lead wires formed on the first surface of the resin film. Each lead wire has an inner lead, an intermediate lead and an outer lead. The inner lead is connected to a corresponding one of the terminals of the semiconductor element. The outer lead is connected to a corresponding external electrode. The intermediate lead is situated between the inner lead and the outer lead. At least said intermediate lead is formed on the first surface of the film. Each outer lead and that portion of the intermediate lead, which is close to the outer lead, is substantially on a level with the external electrode.

Semiconductor device using film carrier

An IC packing device comprises a semiconductor device, a piece of flexible resin film provided with an opening for receiving the semiconductor, wires arranged on the piece of flexible resin film and slits cut into the piece of film from the edges of the opening. The slits cut into the flexible resin film allow the film to be flexed downward toward the semiconductor, along with the wires which to establish electrical connection with the semiconductor. In this manner, the downwardly bent flexible film provides reduction in the possibility of a wire breaking due to excessive bending of the wire in order to make contact with the semiconductor.

Growing community of inventors

Ichikawa, Japan

Hiroshi Tazawa