Fujitsu Corporation

Fujitsu Vlsi Limited

Hiroshi Takase

Takashi Shimizu

Hirotaka Ueno

Kenji Oi

An interface circuit that can disconnect a loop connection among nodes. The interface circuit includes ports, which are connected to bus cables, a state machine and a port controller, which is connected to the ports and the state machine. The state machine determines that a loop connection exists when a process in a predetermined state has been stacked for a predetermined time. When a loop connection exists, the port controller electrically disconnects a port on the loop.

Method of constructing network topology and interface circuit

A packet transfer control circuit is a part of a node in a network of nodes, in which packets of data are passed between the nodes. The packets include normal packets and write packets, and each packet includes a header portion and a data portion. The transfer control circuit includes an identification circuit which identifies if the data portion of a write packet is blank and a processor with a memory connected to the identification circuit. If the write packet is blank, as determined by the identification circuit and the processor is holding data for transmission to another node, the processor puts the data into the data portion of the packet, zero fills if the there is not enough data to fill the data portion, updates the header with the new addressee, and then passes the write packet on to the other nodes.

Packet transfer control circuit

An IEEE 1394 compliant bus controller transfers data packets between connected nodes. The controller includes a processor which divides a series of data into blocks and then stores the blocks in multiple packets (one block per packet). The packets are then transferred over the bus from a source node to a destination node at equal intervals until the entire series of data has been transferred. An initialization prohibition unit prohibits initialization of the nodes during the data transfer which may be caused, for example, by hot plugging (connecting a new node to the bus) during the data transfer.

Device and method for controlling packet transfer

An interface circuit including an interface controller operated by at least a system power supply or an external power supply. A switch is connected between an interface controller and a system power circuit for conducting system power. The interface controller includes a control signal generating circuit for generating a control signal that closes the switch at a timing that does not affect data transmission performed by the interface circuit in accordance with a trigger signal, which indicates that the system power has gone on. Similarly, the switch is opened at a time when data transmission will not be affected.

System power supply control for interface circuit

A protocol controller connected between a SCSI device and a DMA controller. The SCSI device is connected to the protocol controller with a first bus and the DMA controller is connected to the protocol controller with a second bus having a width less than a width of the first bus. The protocol controller communicates with the SCSI device so that it transfers data having a width equivalent to the width of the second bus. Other data concurrently transferred by the SCSI device over the first data bus is ignored and not transferred to the DMA controller.

Method for data width conversion between a DMA controller and an

An improved output circuit that provides an output signal having a predetermined high voltage level regardless of the voltage of a high-potential power supply is described. In one embodiment, the invention includes a first transistor and a second transistor connected in series between a high-potential power supply and a low-potential power supply, and a third transistor connected in parallel to the first transistor between the high-potential power supply and the node between the first and second transistors. The first and second transistors are n-type MOS transistors and the third transistor is a p-type MOS transistor. In another embodiment, the invention further includes a supply voltage detector for detecting a voltage of the high-potential power supply and supplying a voltage signal to the first and third transistors for selectively enabling one of the first and third transistors based on the voltage detected.

Output circuit of semiconductor device

A small computer system interface (SCSI) controller for continuously or intermittently performing communication of plural sets of data. The SCSI controller includes a data register for temporarily storing a set of data, a SCSI interface for transmitting the data stored in the data register in units of 2 bytes and for receiving data from another SCSI controller in units of 2 bytes, a byte counter for counting the number of bytes of data that is transmitted from or received by the SCSI interface, an internal processor for controlling initial setting of a target count value of the byte counter, and a transfer control circuit for controlling transmission of the data stored in the data register from the SCSI interface and reception of data by the data register via the SCSI interface. In data communication in units of 2 bytes, the SCSI controller can prevent transfer of dummy data that is ineffective, to thereby provide efficient data communication.

Transferring digital data in units of 2 bytes to increase utilization of

An output buffer circuit includes a pull-down side transistor connected between an output terminal and a low-potential power source. The pull-down side transistor is driven by an input signal, such that when the pull-down side transistor is turned on by the input signal, a low level output signal is output from the output terminal. A pull-up circuit is connected between the output terminal and a high-potential power source, for changing the output signal to a high level in accordance with the input signal when the transistor is turned off in response to the input signal. The pull-up circuit ceases to function when the output signal goes high thereby creating a high impedance condition. The pull-up circuit includes an OR gate which receives the input signal and the output signal, and an inverter which receives an output signal of the OR gate. A differentiating circuit is provided, through which an output signal of the inverter circuit is output to the output terminal.

Growing community of inventors

Kasugai, Japan

Hiroshi Takase