Kabushiki Kaisha Toshiba

Oki Electric Industry Co., Ltd.

Hiroshi Takamoto

Kenichi Nakamura

Makoto Segawa

Katsuhiro Ishimura

Takayuki Harima

Yasushi Kameda

Shusei Aoki

Takenori Nakamura

Mikio Etou

A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition. Each logical circuit includes a first inverter, a CMOS type second inverter and an N-channel transistor. Each main word line is connected to the input terminals of the first and second inverters. Each section select line is connected to the drain of the N-type transistor and the source of a P-channel transistor of the second inverter. The gate of the N-channel transistor is connected to the output terminal of the first inverter and each section word line is connected to the source of the N-channel transistor and the output terminal of the second inverter. Bit lines are connected to each memory cell for receiving data from a selected memory cell and outputting the data.

Semiconductor memory device for use an apparatus requiring high-speed

Each optical repeater in an optical transmission system includes an optical amplifier, and a control circuit for controlling the optical transmission. Furthermore, each optical repeater transmits management information to the next optical repeater. The control circuit checks the status of the optical amplifier and obtains monitoring information. The control circuit generates management information in accordance with the monitoring information and the management information transmitted from the upstream side optical repeater. The management information is converted to an optical signal and transmitted to the next optical repeater. A receiving station receives the management information. The management information includes an ID code for an optical repeater which has failed and the status of the failure. Different categories of management information have priorities which can be changed by the receiving station, and thus the receiving station can detect the status of the optical transmission line easily and flexibly.

Method and apparatus for alarm surveillance for an optical transmission

A semiconductor integrated circuit has n number of operating circuits that each operate at a predetermined cycle time; n number of wirings that transmit activation signals with respect to said n number of wirings; and a selector drive circuit that sends activation signals to said n number of wirings at respectively different cycle times. By avoiding the simultaneous drive of the operation circuits, the widths of wirings are maintained.

Semiconductor integrated circuit for producing activation signals at

A cascade sense amplifier includes section separated sense amplifiers, a cascade wiring and a main sense amplifier. The main sense amplifier has a capacitance regulation element provided at a base potential of input transistors constituting a data input end. The element is comprised of a metal oxide semiconductor (MOS) transistor for forming a capacitance corresponding to a potential V.sub.SS mainly forming a capacitance by the cascade wiring. A size of the element is determined in the manner that the base potential drop time of the transistors is equal to a potential drop time of the cascade wiring when a power source voltage V.sub.CC drops. Even though the power source voltage V.sub.CC drops, the transistors have no cut-off condition so as to prevent the read-out time from delaying. Especially, if the element is comprised of a MOS transistor, it is possible to use an extremely thin gate insulation layer as a dielectric, thereby suppressing an increase of a chip size.

Cascade sense amplifier for reading out data stored in semiconductor

A semiconductor IC device includes a memory cell group; a pair of bit lines connected to the cell group; plural equalization transistors T.sub.R connected between the bit lines; address transition detectors ATD for detecting changes in address bits; and plural equalizing pulse generating circuits composed of plural logical gates, 15 to 22, respectively and provided for each equalization transistor to generate an equalizing pulse signal to each equalization transistor so that the levels of the two bit lines can be equalized with each other. Since signals outputted from the address transition detectors are synthesized, in particular at a node to which the equalizing pulse signal is applied, the number of logical gate stages to synthesize the detector output signals can be reduced and the wire lengths (e.g. wire capacitances) of the logical gates can be well balanced, thus improving the equalizing speed of the IC device.

Semiconductor integrated circuit device

A semiconductor IC device including a main circuit block and at least one subcircuit block, each having a ground terminal, a supply voltage terminal and an input or output terminal. A first ground line is connected to the ground terminal of the main circuit block and arranged within a wiring domain of the main circuit block and adjacent to the subcircuit blocks. A second ground line is connected to the ground terminal of the subcircuit block and arranged within a wiring domain of the subcircuit block and adjacent to the main circuit block. Protective elements are connected between the first and second ground lines so as to form short circuits through at least one of the first and second ground lines. In the IC device thus configured, all of the input and output terminals resist overvoltage, in every case where any one of the ground terminals and the supply voltage terminals is determined as a reference potential terminal, without complicating the protective element wiring arrangement or increasing the chip area and the cost thereof.

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Tokyo, Japan

Hiroshi Takamoto