Kabushiki Kaisha Toshiba

Hiroshi Takakura

Tetsuya Iida

Junkei Goto

Akira Yamaguchi

Yoshiaki Toyoshima

Yukio Wada

A semiconductor integrated circuit device comprises a semiconductor substrate; an input and output terminal (1) formed on the semiconductor substrate; an input and output circuit (2, 3) formed on the semiconductor substrate, connected to the input and output terminal (1), and having an output buffer (2) of CMOS FETs, supply voltages Vcc1 and Vcc2 being applied to the output buffer; a semiconductor integrated circuit formed on the semiconductor substrate and connected to the input and output circuit; and a circuit for preventing forward junction current from flowing from the input and output terminal (1) to the output buffer (2) when an input voltage exceeding the supply voltages is applied to the output buffer. In an integrated circuit device using a plurality of different supply voltages, it is possible to prevent an input voltage beyond the supply voltages from being applied to the input and output circuit. A voltage switching circuit (4) responsive to signals A and B supplied to an output buffer (2) is interposed between the output buffer (2) and a pad (1). When a voltage higher than the supply voltages is applied to the output buffer (2) from the outside, the substrate potential is determined to a value equal to or higher than the external voltage. Further, the voltage applied from the outside can be also lowered than the supply voltages of the output buffer, before applied to the output buffer.

Semiconductor integrated circuit device having circuitry for limiting

A segment control type D to A converter includes a decoder and a plurality of current source cells. The decoder decodes a digital input signal to generate a control signal. The plurality of current source cells are selected by the control signal output from the decoder. A current output from the selected current source cell is output from an output terminal. Each of the current source cells includes first and second transistors. One terminal of the current path of the first transistor is connected to a constant current source, and the first transistor is ON/OFF controlled such that the gate of the transistor receives the control signal output from the decoder. One terminal of the current path of the second transistor is connected to the other terminal of the current path of the first transistor, and the other terminal of the second transistor is connected to the output terminal. A reference voltage is applied to the gate of the second transistor to cause the second transistor to be normally set in an ON state.

Current source cell use in current segment type D and A converter

Signal sources are arranged in a matrix form and provide preset analog values. Switching means are connected between signal sources and an analog output terminal having connection paths to the respective signal sources. Latch circuits are respectively provided for switch control circuits for controlling the switching means. Each of the latch circuits latches a control signal from a corresponding one of the switch control circuits and outputs the control signal in response to a preset synchronizing signal to a corresponding one of the switching means. The switching means are simultaneously controlled by output signals of decoders so that a desired analog output is permitted to be derived from the output terminal. The period of the clock signal can be shorten and a switching operation causing variation exceeding a desired variation occurring when the digital signal is changed can be prevented.

Digital to analog converter

A signal interference prevention wiring is disposed between two wirings which are arranged in parallel for transmitting a signal, and the signal interference prevention wiring is held at a constant potential.

Growing community of inventors

Kawasaki, Japan

Hiroshi Takakura