Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Hiroshi Sonobe

Akihiro Suzuki

Atsuhisa Kageyama

Satoru Tanigawa

Hisao Kunitani

Keisuke Kodera

Tomomitsu Masuda

Masayuki Motohama

In a semiconductor integrated circuit, one of two signals generated from a first logic circuit is delayed in a first delay addition circuit, looped back by an input/output terminal, and then inputted to a second logic circuit. The other output of the first logic circuit is looped back by a reference input/output terminal, further delayed in a second delay addition circuit, and then inputted to the second logic circuit. By varying respective amounts of delay added by the first and second delay addition circuits from each other, AC timing specifications are satisfied and it is determined whether or not the semiconductor integrated circuit has passed a test based on whether or not the output of the second logic circuits is a desired signal relative to the input of the first logic circuit.

Circuit for testing the AC timing of an external input/output terminal of a semiconductor integrated circuit

A clock generation apparatus is provided with a frequency phase error calculation circuit, whereby a clock synchronized with burst lock and a line lock clock can be simultaneously generated by a DTOon the basis of frequency information of a DTOand phase error information from a phase comparatorand a digital LPF. Therefore, the clock generation apparatus can cope with a system that required plural clocks, and frequency spread is easily carried out by generating spread information by a frequency spread information generation circuit, and adding it in the DTO. As a result, interference to a video terminal from the clock can be reduced, and performance of a video terminal such as a television receiver can be exploited.

Clock generation apparatus

A synchronous clock generation apparatus including a multiplier for multiplying a horizontal synchronizing signal by a horizontal synchronizing pulse signal to generate multiplication data, a gain variable digital LPF for extracting only DC components from the multiplication data and capable of performing gain adjustment, and a controller for calculating gain adjustment data, lock center frequency setting data, and LPF gain adjustment data based on the correction data. The controller detects an amount of deviation from the lock center frequency and an amount of variation, displaces the lock center frequency and shifts the lock range along the frequency axis to enlarge the apparent lock range when the amount of deviation is large, and reduces the gain to improve lock precision when the amount of variation is small, without expanding bits in the circuit configuration.

Synchronous clock generation apparatus and synchronous clock generation method

In a semiconductor device of the present invention, a clock is not changed instantaneously but it is changed over maximum N+1/M clocks (N: integer not less than 2) by shifting delay cells in a step by step manner to make the phase state of a previous reference signal and the phase state of a present reference signal coincide with each other, whereby the clock is synchronized with the reference signal with accuracy, and the duty of the output clock is kept constant. With this semiconductor device, it is possible to prevent the duty of the clock from being discontinuous when a signal whose reference signal does not coincide with the clock is inputted and reset is made to a rising edge of this reference signal.

Semiconductor device

The present invention provides a semiconductor inspection method which detects a short circuit failure of adjacent lines having the possibility of a short circuit occurring, which short circuit failure cannot be detected by the conventional semiconductor inspection methods. The semiconductor inspection method comprises steps of: extracting adjacent lines having the possibility of a short circuit occurring between the lines from a layout patter of a semiconductor (step S), obtaining input logical values such that one of the adjacent lines has a logical value '1' while the other has a logical value '0' (step S), and monitoring outputs of a logical circuit which receives the input logical values, thereby to compare the outputs with output logical values which are expected when the input logical values are input to the logical circuit (step S). Therefore, the short circuit failure of the adjacent lines in the logical circuit can be correctly detected in a short time.

Semiconductor inspection method

A semiconductor device that generates a clock which is synchronized with a reference signal stably and with fixed synchronization accuracy, and enables to deal with an abrupt variation in the reference signal. This semiconductor device includes N stages of delay elements each delaying an external clock by 1/N clock (N: an integer that is two or larger); a phase comparator for comparing the phase of a clock that has been delayed by the N stages of the delay elements with the phase of the external clock one clock late; a controller that receives a phase difference detected by the phase comparator and controls respective delays of the delay elements; and a selector for selecting a delayed clock having the closest phase to the reference signal from delayed clocks which are generated by the N stages of the delay elements, respectively, and shifted in phase with each other by 1/N clock.

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Osaka, Japan

Hiroshi Sonobe