Renesas Electronics Corporation

Renesas Technology Corp.

Mitsubishi Electric System Lsi Design Corporation

Mitsubishi Electric System

Lsi Design Corporation

Hiroshi Shirota

Ryosuke Okuda

Kazuyuki Ito

Katsuya Mizumoto

Kazuaki Tanida

Tadashi Saito

Masao Aramoto

If an exclusive OR circuit itself, a component of a signal delay detecting circuit, has failed to operate properly, a signal delay cannot be detected accurately. A malfunction pre-detecting circuitincludes a delay circuit DL to delay input data that is input in parallel to a data input terminal of a flip-flop FFprovided in a subsequent stage of a flip-flop FF, a flip-flop FFT that receives output of the delay circuit DL, and a comparator CMP that compares output of the flip-flop FFand output of the flip-flop FFT. Test data tvand test data tvare input to the malfunction pre-detecting circuitin an operation test mode for testing operation of the malfunction pre-detecting circuit. The test data tvis input to the delay circuit DL. The comparator CMP compares the test data tvand output of the flip-flop FFT in the operation test mode.

Semiconductor device

This invention provides a digital broadcasting receiving unit capable of achieving synchronization of time information between a base station and a receiving unit with reference clock without use of a crystal oscillator (VCXO) having a variable frequency. The crystal oscillator oscillates a clock of a predetermined fixed frequency. A variable digital dividing circuit divides a fixed frequency by a division ratio so as to change the division ratio. A system decoder detects reference time information from the base station. A reference counter generates time information of a receiving unit. A phase comparator detects a difference between reference time information and time information. A division ratio control circuit controls the change of the division ratio based on the difference. The reference counter generates time information based on a clock having a frequency obtained by dividing by the variable digital dividing circuit and feeds back time information to the phase comparator.

Digital broadcasting receiving unit and digital broadcasting system

A FIFO circuit includes a write counter circuit, a memory circuit, a read counter circuit and a selector circuit. The write counter circuit counts a write clock signal during a valid period of input data, and outputs a write counter value. The memory circuit stores the input data in response to the write counter value. The read counter circuit counts a read clock signal when a decision is made that the memory circuit includes data that has not yet been read out, and outputs a read counter value. The read selector circuit reads data from the memory circuit in response to the read counter value. A small scale FIFO circuit can be obtained.

High speed, low current consumption FIFO circuit

A data/clock recovery circuit can recover high-rate data using the data as a clock signal. It includes an edge detector, a clock selection signal generating circuit, a clock selection circuit and a synchronizing circuit. The edge detector generates edge position information using a receiver output as a clock signal. The clock selection signal generating circuit generates a clock selection signal in response to the edge position information using the receiver output as the clock signal. The clock selection circuit selects a recovered clock signal from a clock signal group in response to the clock selection signal. The synchronizing circuit synchronizes the receiver output using the recovered clock signal, and outputs it as a synchronized data signal.

Data/clock recovery circuit for recovering data and clock signal with high accuracy

The number of pulses of a clock signal CLK-A is circularly counted in a count range from '0' to '7', and count signals indicating count values are produced. A clock signal CLK-B having a frequency lower than that of the clock signal CLK-A is produced from count signals of &#x201c;3&#x201d; and &#x201c;7&#x201d;, and data transfer between a high speed operating block operated in synchronization with the clock signal CLK-A and a low speed operating block operated in synchronization with the clock signal CLK-B is performed in synchronization with the clock signal CLK-B to receive input serial data or transmit output serial data. When a stuff bit of universal Serial Bus is detected in the input serial data or is inserted in the output serial data, a cycle of the clock signal CLK-B is lengthened by one cycle of the clock signal CLK-A.

Growing community of inventors

Tokyo, Japan

Hiroshi Shirota