Kabushiki Kaisha Toshiba

Mitsubishi Electric Corporation

Tokyo Shibaura Denki Kabushiki Kaisha

Hiroshi Shigehara

Masanori Kinugasa

Toshinobu Hisamoto

Akira Yamaguchi

Akira Takiba

Fuminari Tanaka

Toshimasa Kawaai

Hidemi Iseki

Mikio Shiraishi

Yasunori Tanaka

Takao Nakajima

Yasuhiro Watanabe

Tsuyoshi Sempuku

Satoshi Nonaka

Yoshihiro Iwamoto

Yoko Sano

Makoto Otsuru

Kotoyu Sasayama

Nobuo Sugi

Ryuji Fujiwara

Ryouichi Isohata

Kenichi Matsumoto

Junya Masumi

Koichi Satoh

Hirokata Ohta

A navigation device includes a road periphery display change unitthat selects a road R which connects to, intersects with, or is adjacent to a guidance route/a travel plan routefrom a map database, and displays the road in a high contrast on the inside of a predetermined distance from the guidance route/the travel plan route, displays the road in a low contrast on the outside of the predetermined distance, and displays the road by changing continuously or stepwise a gradation in an intermediate region between the inside and the outside.

Navigation device

Two terminals of each of transistors (P , N ) are connected between two terminals (A, B). A body effect compensation circuit (COMP-P ) for the transistor (P ) and a body effect compensation circuit (COMP-N ) for the transistor (N ) are arranged. The back gates of transistors (P P, P P) in the circuit (COMP-P ) and transistors (P N, P N) in the circuit (COMP-N ) are commonly connected to the back gate of the transistor (P ). The back gates of transistors (N N, N N) in the circuit (COMP-N ) and transistors (N P, N P) in the circuit (COMP-P ) are commonly connected to the back gate of the transistor(N ). With this structure, in transferring a signal from one terminal (A or B) to the other terminal (B or A) or vice verse, the signal potential is transferred to the back gates of the transistors (P , N ) at a high speed to increase the signal transfer speed.

Transmission gate

Two terminals of each of transistors (P , N ) are connected between two terminals (A, B). A body effect compensation circuit (COMP-P ) for the transistor (P ) and a body effect compensation circuit (COMP-N ) for the transistor (N ) are arranged. The back gates of transistors (P P, P P) in the circuit (COMP-P ) and transistors (P N, P N) in the circuit (COMP-N ) are commonly connected to the back gate of the transistor (P ). The back gates of transistors (N N, N N) in the circuit (COMP-N ) and transistors (N P, N P) in the circuit (COMP-P ) are commonly connected to the back gate of the transistor (N ). With this structure, in transferring a signal from one terminal (A or B) to the other terminal (B or A) or vice verse, the signal potential is transferred to the back gates of the transistors (P , N ) at a high speed to increase the signal transfer speed.

An output circuit for a semiconductor integrated circuit includes an output terminal, a first NMOS transistor having one end of a current path between a drain and a source thereof connected to a first node, having a control signal input a gate thereof, and having the other end of the current path connected to a ground potential node, a second NMOS transistor having one end of a current path between a drain and a source thereof connected to the first node and the other end connected to an output terminal, a PMOS transistor and an NMOS transistor connected between a second node that is a gate of the second NMOS transistor and the output terminal, to act as capacitance elements, and a pull-up element connected between the second node and the node of the power potential.

Output circuit for semiconductor integrated circuit

Either the power-supply potential or a ground potential is applied to a power-supply node through a switch. When a potential higher than the ground potential is applied to the output terminal while an power-supply node is connected to the ground-potential node, the potential of a back gate of a first PMOS transistor incorporated in an output section increases in accordance with the potential of the output terminal, due to the pn-junction provided between a drain and back gate of the first PMOS transistor. At this time, a second PMOS transistor whose source-drain path is connected between the back gate and gate of the first PMOS transistor is turned on, whereby the potential of the back gate of the first PMOS transistor is transferred to the gate thereof.

MOS output buffer with overvoltage protection circuitry

When a power supply terminal (,) is grounded, a circuit (,) is in the OFF state, and a high potential is transferred from a circuit (,) to a bus line (BL), the high potential is transferred to a node (,) via the source of a transistor (P,), back gate (Nw), and transistor (P,). A NAND circuit (NA,) always outputs a control signal (VGP) of a level equal to the node (,) to the gate of the transistor (P,) to turn non-conductive the transistor (P,). Hence, a current path from a terminal (B) to a terminal (A) or from the terminal (B) to the back gate (Nw) is cut off to prevent wasteful current consumption.

Transmission gate circuit

Two terminals of each of transistors (P,, N,) are connected between two terminals (A, B). A body effect compensation circuit (COMP-P,) for the transistor (P,) and a body effect compensation circuit (COMP-N,) for the transistor (N,) are arranged. The back gates of transistors (P,P, P,P) in the circuit (COMP-P,) and transistors (P,N, P,N) in the circuit (COMP-N,) are commonly connected to the back gate of the transistor (P,). The back gates of transistors (N,N, N,N) in the circuit (COMP-N,) and transistors (N,P, N,P) in the circuit (COMP-P,) are commonly connected to the back gate of the transistor (N,). With this structure, in transferring a signal from one terminal (A or B) to the other terminal (B or A) or vice verse, the signal potential is transferred to the back gates of the transistors (P,, N,) at a high speed to increase the signal transfer speed.

Either the power-supply potential or a ground potential is applied to a power-supply node through a switch. When a potential higher than the ground potential is applied to an output terminal while the power-supply node is connected to the ground-potential node, the potential of a back gate of a first PMOS transistor incorporated in an output section increases in accordance with the potential of the output terminal, due to a pn-junction provided between the drain and back gate of the first PMOS transistor. At this time, a second PMOS transistor whose source-drain path is connected between the back gate and gate of the first PMOS transistor is turned on, whereby the potential of the back gate of the first PMOS transistor is transferred to the gate thereof.

In a case where a plurality of outputs are connected and used, even when a voltage higher than the power-supply voltages inside the integrated circuit is applied to the signal output terminal, the reliability of the internal elements is prevented from deteriorating. The semiconductor integrated circuit includes a PMOS transistor that has its source potentially isolated from its back gate and has one end of the current path between its source and drain connected via a transistor switch to the signal output terminal. The integrated circuit generates a control signal having a value proportional to the voltage at one end of the current path between the source and drain of the PMOS transistor, supplies the generated control signal to the gate of the PMOS transistor, and controls the voltage of the control signal so that the potential difference between one end of the current path between the source and drain and the gate of the PMOS transistor may be within a desired range of values when the PMOS transistor is set in the on state by the control signal.

Output circuit providing protection against external voltages in excess

A semiconductor device of the present invention comprises: a semiconductor substrate of a first conductive type; a gate electrode formed on the semiconductor substrate; a first semiconductor region of a second conductive type different from the first conductive type, the first semiconductor region being formed on the semiconductor substrate in one of both side regions of the gate electrode so as to be adjacent to the gate electrode; a second semiconductor region of the second conductive type formed on the semiconductor substrate in the other region of the both side regions of the gate electrode so as to be adjacent to the gate electrode; a third semiconductor region of the second conductive type formed in the one region so as to be isolated from the first semiconductor region and to be spaced from the second semiconductor region by a greater distance than that between the first and third semiconductor regions; a connecting portion for connecting the first semiconductor region to the third semiconductor region, the connecting portion having a higher resistance than those of the first and third semiconductor regions; a first electrode formed so as to be electrically connected to the third semiconductor region; and a second electrode formed so as to be electrically connected to the second semiconductor region. Thus, it is possible to prevent the element characteristics from deteriorating even if a surge voltage is applied and to decrease the element size.

Semiconductor device

Two terminals of each of transistors (P1, N1) are connected between two terminals (A, B). A body effect compensation circuit (COMP-P1) for the transistor (P1) and a body effect compensation circuit (COMP-N1) for the transistor (N1) are arranged. The back gates of transistors (P1P, P2P) in the circuit (COMP-P1) and transistors (P1N, P2N) in the circuit (COMP-N1) are commonly connected to the back gate of the transistor (P1). The back gates of transistors (N1N, N2N) in the circuit (COMP-N1) and transistors (N1P, N2P) in the circuit (COMP-P1) are commonly connected to the back gate of the transistor (N1). With this structure, in transferring a signal from one terminal (A or B) to the other terminal (B or A) or vice verse, the signal potential is transferred to the back gates of the transistors (P1, N1) at a high speed to increase the signal transfer speed.

Transmission gate including body effect compensation circuit

In a situation where another analog switching circuit 502 outputs a high potential Vh, this high potential Vh is applied to an output terminal OUT1 of an analog switching circuit 504. When a ground potential is supplied to a node 10 with a changeover switch SW, a diode DD1 falls to an inversely biased state, whereby a potential at a backgate node Nw comes to be approximately equal to the potential Vh. Moreover, a potential approximately equal to the potential Vh is a power source terminal of an NAND gate NAND1, and it is transmitted to an output terminal VGP through an internal circuit, whereby a P channel MOS transistor P1 is turned off. Moreover, the output VGP from an inverter INV5 makes also an N channel MOS transistor N1 turn off. With such a constitution, an unnecessary current is prevented from flowing from a power source potential terminal on a bus line and so on to a ground potential terminal through a parasitic diode, thereby performing full-swinging without lowering an output level.

Analog switching circuit device and semiconductor integrated circuit

Either a power-supply potential or a ground potential is applied to a power-supply node through a switch. When a potential higher than the ground potential is applied to an output terminal while the power-supply node is connected to the ground-potential node, the potential of a back gate of a first PMOS transistor incorporated in an output section increases in accordance with the potential of the output terminal, due to a pn-junction provided between the drain and back gate of the first PMOS transistor. At this time, a second PMOS transistor whose source-drain path is connected between the back gate and gate of the first PMOS transistor is turned on, whereby the potential of the back gate of the first PMOS transistor is transferred to the gate thereof.

To an input terminal is connected one end of the source-to-drain current path of an NMOS the gate of which is connected to Vcc. The other end of the current path of the NMOS is connected by a protection circuit comprised of a PMOS and an NMOS to the common gates of a PMOS and an NMOS in the input stage of an internal circuit. In the protection circuit, the PMOS has its source and gate connected to Vcc and its drain connected to the common gates of the PMOS and the NMOS, while the NMOS has its source and gate connected to Vss and its drain connected to the common drains of the PMOS and the NMOS.

Interface circuit for use in a semiconductor integrated circuit

An output circuit comprising an output stage and a control signal generator. The output stage is constituted by a first P-channel MOS transistor and an N-channel MOS transistor. The control signal generator generates a signal for driving the gates of the MOS transistors, it comprises a NAND gate, a NOR gate NOR1 and an inverter INV1. The first P-channel MOS transistor of the output stage has a source and a back gate which are isolated in terms of potential. A second P-channel MOS transistor is provided, whose source-drain path is connected between the back gate and gate of the first P-channel MOS transistor incorporated in the output stage.

Growing community of inventors

Tokyo, Japan

Hiroshi Shigehara