Kawasaki Steel Corporation

Hiroshi Sasama

Masato Yoneda

Naoki Kanazawa

Masahiro Konishi

Ryuichi Hata

An associative memory to which an encoder is applied has a plurality of associative memory subblocks each having a plurality of memory words. A hit flag resulting from match retrieval of retrieval data and the contents of the memory word, and an empty flag indicating whether or not the contents of the memory word are valid as objects for match retrieval are output from each memory word of each associative memory subblock. The address of an invalid memory word is readily controllable since the address of the memory word corresponding to the empty flag can be output as in a case where the address of the memory word corresponding to the hit flag is output. Moreover, since the hit flag and the empty flag are allowed to share a detection line with each other for common use in this encoder, the layout area of the associative memory is reduced and it is possible to build up a high-density associative memory.

Hierarchical encoder including timing and data detection devices for a content addressable memory

Hierarchical encoder including timing and data detection devices for a

An associative memory device in which a coincident output is held by each word and aging for word data can be efficiently performed such that the word data is made valid or invalid on the basis of the information. The associative memory device includes a plurality of words for storing data, for detecting the coincidence/non-coincidence between the data stored in the plurality of respective words and input search data. Each word further includes a memory for storing a coincidence line output by a searching operation, a storage memory for storing data representing whether the corresponding word is subjected to a searching operation or is available to write new data therein, a circuit for simultaneously setting/resetting the contents of the storage memory, and circuit for resetting/setting the memory for storing the coincidence line output by the storage memory.

Associative memory device having circuitry for storing a coincidence

The associative memory may include a plurality of memory words storing storage data, flag registers each corresponding to an associated one of the plurality of memory words, a gate circuit having signal lines each corresponding to an associated one of the plurality of memory words and a priority encoder for designating one of the memory words. An address converter may convert the address of one of the memory words output from the priority encoder into a representative address. The storage data may include a pair of attribute indicative of positioning in the data group to which the storage data belongs. In at least one embodiment, match lines each corresponding to an associated one of the plurality of memory words and a plurality of encode coding circuits may be provided.

Associative memory to retrieve a plurality of words

This invention provides an associative memory that includes a plurality of associative memory integrated circuits. Each of the associative memory integrated circuits includes a plurality of memory words and a data registration device. The data registration device stores a retrieval word into one of the plurality of memory words in response to control signal received from an external source if a first priority signal is not received from at least another one of the plurality of associative memory integrated circuits and if the one of the plurality of memory words is in an open state.

Associative memory having a data registration device

A encoder has a prefetch circuit or a flag data sense circuit built into the priority encoder provided for a CAM block. While a hit signal in the first priority subblock is being encoded, a hit signal in the second priority subblock can be stored in the prefetch circuit. Therefore, the encoding operation is performed without subblock-to-subblock switch time and this makes the encoder best suitable for a large capacity CAM which is required to operate at high speed. Moreover, a semiconductor integrated circuit of the present invention detects the differential current between the current flowing through one signal line and the reference current flowing through the other signal line. Moreover, it can operate as the number detection circuit to detect the number of hit signal in the subblock, and it can operate as the timing control circuit to previously notify the encode termination of the hit signal in the subblock of the encoder described above. Therefore, this semiconductor integrated circuit can allow the encoder to encode very efficiently at high speed. Moreover, a dynamic sense amplifier is able to operate with a great operating margin.

A Content Addressable Memory (CAM) encoder comprises either a prefetch circuit or a flag data sense circuit. While a hit signal in the first priority subblock is being encoded, a hit signal in the second priority subblock can be stored in the prefetch circuit. Therefore, the encoding operation is performed without subblock-to-subblock switch time and enables a large capacity CAM to operate at high speeds. Moreover, a semiconductor integrated circuit detects the differential current between the current flowing through a first signal line and the reference current flowing through a second signal line. Moreover, it can operate as the number detection circuit to detect the number of hit signal in the subblock and operates as the timing control circuit to predict the termination of the encoding operation. Therefore, this semiconductor integrated circuit can allow the encoder to encode very efficiently at high speed.

In an associative memory comprising a function to extend data width, for which match retrieval is to be conducted, up to a plurality of words, that is, a function to detect total match data when match is respectively detected for a plurality of continuous retrievals, power consumption can be reduced by making active only the necessary areas under the condition that the whole circuit is no longer required to be made active through execution of the current retrieval only to the blocks for which match is detected in the preceding retrieval during a plurality of continuous retrieving operations and/or its adjacent blocks.

Associative memory

A priority encoder is provided with priority circuitry for sequentially producing priority-ordered output signals and encoding circuitry for encoding the output signal. Small input, small unit priority circuits are used to form the priority circuitry into a hierarchical structure. An OR output of a small unit priority circuit in a lower hierarchy is used as an input signal of another small unit priority circuit in a higher hierarchy. An output signal of the priority circuit in the higher hierarchy has an address which corresponds to the address of the one input signal and is made an enable signal of the priority circuit in the lower hierarchy. The priority encoder, though simple in structure and formed with a small number of elements, operates at a high speed. Moreover, an encoder with a prefetch circuit is built into the priority encoder provided for a CAM block. While a 'hit' signal in a first priority subblock is being encoded, a hit signal in a second priority subblock can be stored in the prefetch circuit. Therefore, the encoding operation is performed without subblock-to-subblock switch time, making the encoder best suitable for a large capacity, high speed CAM.

Priority encoder applicable to large capacity content addressable memory

An associative memory wherein unnecessary data may be exclusively erased on a batch basis. Each word memory in the associative memory has a corresponding first flag which indicates whether or not effective data is stored in the memory and a second flag which indicates of whether or not a match has been detected. The first flags are reset on a batch basis in accordance with the state of the associated second flags.

An associative memory is capable of performing at high speed a registration of unregistered data. Retrieval data is stored at the same time when a retrieval is carried out.

Growing community of inventors

Tokyo, Japan

Hiroshi Sasama