Fujitsu Corporation

Hiroshi Okano

Atsuhiro Suga

Yoshio Hirose

Fumihiko Hayakawa

Teruhiko Kamigata

Hitoshi Yoda

Hideo Miyake

Shigetoshi Wakayama

Taizo Sato

Yasuki Nakamura

Yoshimasa Takebe

Yasuhiro Yamazaki

Atsuki Inoue

Shin-ichiro Tago

A semiconductor integrated circuit includes: a floating point arithmetic unit that includes circuit resources over which power saving control is performed, and executes a floating point arithmetic operation; a power-control instruction control unit that receives a pre-access instruction corresponding to a floating point arithmetic operation instruction, and invalidates stepwise the power saving control over the circuit resources included in the floating point arithmetic unit to operate a part of the circuit resources in the floating point arithmetic unit; and a control unit that causes the floating point arithmetic unit to execute the floating point arithmetic operation, wherein before execution of the floating point arithmetic operation in the floating point arithmetic unit, power consumption is previously increased by the pre-access instruction.

Semiconductor integrated circuit and compiler

A semiconductor integrated circuit includes a user circuit and a power supply noise suppression circuit. The user circuit includes a plurality of circuit modules each containing an operation ratio control circuit. The power supply noise suppression circuit judges an amount of current fluctuation occurring in the user circuit by monitoring an operation ratio of each of the plurality of circuit modules, and controls, via each of the operation ratio control circuits, the operation ratio of a corresponding one of the circuit modules in accordance with a result of the judgment of the amount of current fluctuation.

Semiconductor integrated circuit and control method for the same

A power supply voltage adjusting apparatus includes a voltage setting part that, according to a characteristic variation of a semiconductor integrated circuit, sets a first power supply voltage of a first power supply domain module among a plurality of modules in the semiconductor integrated circuit, each module respectively having a different power supply voltage; a detecting part that compares phases of a first clock signal flowing through the first power supply domain module and a second clock signal flowing through a second power supply domain module to detect a phase difference; and a voltage adjusting part that adjusts a second power supply voltage supplied to the second power supply domain module to reduce the phase difference detected by the detecting part.

Power supply voltage adjusting apparatus, recording medium, and power supply voltage adjusting method

A semiconductor integrated circuit includes: an internal circuit; a detecting circuit which detects an element characteristic of the internal circuit; a calculating circuit which calculates a first consumption energy consumed when a power gating operation is performed on a task processed by the internal circuit and a second consumption energy consumed when an operation of reducing a voltage and a frequency is performed in accordance with the element characteristic; and a switching circuit which performs the power gating operation on the internal circuit when the first consumption energy is smaller than the second consumption energy and performs the operation of reducing a voltage and a frequency when the second consumption energy is smaller than the first consumption energy.

Semiconductor integrated circuit

In a semiconductor integrated circuit including plural types of transistors having different threshold voltages, a plurality of oscillators including respective types of transistors are provided. The respective oscillation frequencies of these oscillators are counted, and based on the count values, a voltage to be set on a power supply voltage device for the semiconductor integrated circuit is determined according to the count values.

Power supply voltage adjusting device

An an address generator generates a read address. It is detected whether the generated read address is continuous to the read address previously generated. A cache unit control circuit controls the read data to be directly output to a requester of the read data without passing the read data through a cache RAM, if a cache miss occurs, and if it has been detected that the two addresses are continuous. As a result, the subsequent operations can executed even if the present operation has not been completed.

Arithmetic processor

An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which assigns a read address to the instruction store portion, an instruction buffering portion which includes a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion. A branching instruction detection portion detects a branching instruction in the instruction sequence read from the instruction store portion. A branch target address information buffering portion includes a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction.

Processing device for buffering sequential and target sequences and target address information for multiple branch instructions

A circuit for data transfer includes a first buffer operating at a first clock frequency, a plurality of second buffers operating at a second clock frequency, and a selector circuit which receives data at the first clock frequency, and supplies the data to a selected one of the first buffer and the second buffers.

Data transfer circuit between different clock regions

In an information processing device, a first address adder generates a first address representing a target for write of data or a storage location of data to be read. A second address adder generates a second address by adding 8 to the first address. First to seventh selectors appropriately select either the first address or the second address, and supply the selected address to first to seventh memory areas, respectively. An eighth memory area is supplied with the first address.

Device and method for information processing

In a cache memory control method and computer of the present invention, a cache memory is connected to a main memory and divided into a plurality of cache blocks, and a lock/unlock signal is supplied to the cache memory to either set a replace-inhibition state of at least one of the cache blocks in which replacing at least one of the cache blocks to the main memory is inhibited, or reset the replace-inhibition state of at least one of the cache clocks such that replacing at least one of the cache block to the main memory is allowed. Either reading or writing of the main memory is performed by using the remaining cache blocks of the cache memory, other than the at least one of the cache blocks, such that, when the replace-inhibition state is set by the lock/unlock signal, replacing the at least one of the cache blocks to the main memory is inhibited during the reading or writing of the main memory.

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Kawasaki, Japan

Hiroshi Okano