Hitachi, Ltd.

Other

Renesas Technology Corp.

Hitachi Ulsi Engineering Corp.

Hiroshi Ohsuga

Yasushi Akao

Kiyoshi Matsubara

Atsushi Hasegawa

Kouki Noguchi

Keiichi Kurakazu

Shumpei Kawasaki

Yoshitaka Ito

Akio Hayakawa

Shiro Baba

Toru Baji

Atsushi Kiuchi

Koki Noguchi

Hironobu Hasegawa

A built-in memory is divided into the following two types: first memoriesandand second memoriesand, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU corecan simultaneously transfer two data values from the built-in memory to a DSP engine. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU corecan access an external memory in parallel with the access to the second memoriesandand the first memoriesand

Microcomputer

A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory

Single-chip microcomputer with hierarchical internal bus structure having data and address signal lines coupling CPU with other processing elements

Processing system with microcomputers each operable in master and slave modes using configurable bus access control terminals and bus use priority signals

A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and

Microprocessor having a DSP and a CPU and a decoder discriminating between DSP-type instructions and CUP-type instructions

A built-in memory is divided into the following two types: first memories and and second memories and , and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core can simultaneously transfer two data values from the built-in memory to a DSP engine . Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core can access an external memory in parallel with the access to the second memories and and the first memories and

Microcomputer system with at least first and second microcomputers each operable in master and slave modes with configurable bus access control terminals and bus use priority controller

Single-chip microcomputer synchronously controlling external synchronous memory responsive to memory clock signal and clock enable signal

Single-chip microcomputer operable in master and slave modes and having configurable bus control terminals

Microcomputer having multiple bus structure coupling CPU to other

A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

Growing community of inventors

Hino, Japan

Hiroshi Ohsuga