Hitachi, Ltd.

Hiroshi Ohguro

Hiroshi Iwamoto

Takeshi Aimoto

Takehisa Hayashi

Kenichi Kurosawa

Satoshi Yoshizawa

Hidenori Inouchi

Tetsuaki Nakamikawa

Hideki Murayama

Kazuhiro Hashimoto

Haruyuki Nakayama

Shoichi Murase

Shinichi Tanabe

Kenji Nakajima

Michio Morioka

Yoshihiro Miyazaki

Shinichiro Yamaguchi

Shin Kokura

Koichi Ikeda

Takaaki Nishiyama

A data communication system for a computer system in which a plurality of computers are mutually connected includes: a plurality of computers each having an area to store a command to execute a data communication on the basis of it and a buffer area to store data; a switch circuit to mutually selectively connect the plurality of computers; and a transmission permitting component, connected between the switch circuit and one of the plurality of computers, for outputting a signal to permit the data transmission from such one computer to such another computer; a communication component for transmitting the data received from such one computer by outputting the transmission permission signal from the transmission permitting component to such another computer through the switch circuit; a detecting component to detect the occurrence of an abnormality regarding the data communication from such one computer to such another computer; and a communication control component to abandon the data that is subsequently received from such one computer by outputting the transmission permission signal in accordance with an output of the detecting component. When the abnormality occurs, the switch circuit releases such another computer, thereby disconnecting such one computer and such another computer. When reception commands prepared in the buffer area of such another computer are perfectly used, such another computer abandons the packet which does not include the flag to instruct the continuous reception.

Network for mutually connecting computers and communicating method using

A dual computer system consisting of two computer systems connected by a plurality of data transfer units and a plurality of data transfer channels for a memory copy made to again synchronize both the computer systems at the time of recovery from a fault. When no fault occurs on the data transfer channels, the data transfer units share the load of data transfer in the memory copy operation, and when a fault occurs on any data transfer unit during the memory copy operation, the remaining normal data transfer units are used to again transfer data, whereby a memory copy is made at high speed for again synchronizing both the computer systems at the time of recovery from a fault, and system reliability at the time of recovery from a fault is improved.

Dual information processing system having a plurality of data transfer

A data communication system for a computer system in which computers are mutually connected includes: each computer having an area to store a command to execute data communication on the basis of it and a buffer area to store data; a switch circuit to mutually selectively connect the computers; and a transmission permitting component, connected between the switch circuit and one of the computers, for outputting a signal to permit the data transmission from one computer to another computer; a communication component for transmitting the data received from one computer by outputting the transmission permission signal from the transmission permitting component to another computer through the switch circuit; a detecting component to detect the occurrence of an abnormality regarding the data communication from one computer to another computer; and a communication control component to abandon the data that is subsequently received from one computer by outputting the transmission permission signal in accordance with an output of the detecting component. When the abnormality occurs, the switch circuit releases another computer, thereby disconnecting one computer and another computer. When reception commands prepared in the buffer area of another computer are perfectly used, another computer abandons the packet which does not include the flag to instruct the continuous reception.

A highly reliable computer system is intended to duplicate processors, compare the outputs of the processors with each other and enhance the validity of the output of processor system. If a mismatch between the outputs is detected, one of the processors performs a process of saving an internal state of the processor in amain memory and diagnosing factor of the detected mismatch. If the process is recognized to be continued in a duplex mode, the processors are re-synchronized by a processor reset, and initialize themselves and restore the internal information saved in the main memory for continuing the process having been proceeded before the fault occurred.

Fault recovering system provided in highly reliable computer system

Growing community of inventors

Hadano, Japan

Hiroshi Ohguro