Rohm Co., Ltd.

Hiroshi Nozawa

Yoshikazu Fujimori

Shinzo Koyama

Masao Takayama

Akira Kamisawa

Yoshiro Fujii

Hiroaki Kato

Keikichi Tamaru

The present invention aims at providing a novel enciphering and deciphering apparatus and an enciphering and deciphering method related thereto, which are respectively capable of contracting the time required for enciphering and deciphering processes and decreasing the number of logic gates provided in the apparatus. Essentially based on an equation X=1+&#x3a3;((J=1, i)C&#xb7;X) and also based on an initial value consisting of a group of power raising values Xcorresponding to j=1 through m in relation to k&#x2212;1=k0, an arithmetic operating unit 21 seeks a second expression Yby serially computing a group of power raising values Xcorresponding to i=1 through m in relation to one unit of k shown in the above equation in a range from k=k0+1 up to k=k1 by applying binomial coefficients stored in a coefficient memory unit. Accordingly, once those binomial coefficients corresponding to predetermined integers n and m are stored in memory, thenceforth, it is possible to contract the time required for executing an enciphering or deciphering process related to identical integers n and m.

Enciphering and deciphering apparatus, and enciphering and deciphering method

A switch circuit that is simple in constitution and capable of reliably controlling a switch cell is provided. Since the, gate terminal Gof a transistor Min a switch cell SC is connected only to the terminalof a transistor M, when the transistor Mis set to off, the moving path of the charge accumulated at the gate Gof the transistor Mis shut off. Consequently, even if the transistor Mis set to an on state and immediately set back to an off state, the transistor Mremains for some period of time in an on or off state corresponding to the switching data given through a bit line BL. It is possible to cause the transistor Mto remain in an on or off state for a specified period of time without disposing a specific circuit for temporary storing the switching data.

Switch matrix circuit, logical operation circuit, and switch circuit

A coding-decoding device and a coding-decoding method that take less time for coding and decoding are provided while using less number of logic gates. A memory devicesubstantially stores b pieces of conversion logic equations produced with a conversion logic equation producing device. An operation devicehas a programmable hardware logic circuit to constitute logics sequentially according to plural execution unit logic equations obtained by dividing b pieces of conversion logic equations stored in the memory deviceinto execution units for respective execution unit logic equations using the hardware logic circuit. Besides, the operation devicesequentially divides and calculates the second sentences from the first sentences according to the constituted logics. An output devicecollects and outputs the second sentences calculated with the operation device

Coding-decoding device and method for conversion of binary sequences

To provide a memory device with a function to perform an operation and a method of performing an operation and storage which can save space and cost and which can start, immediately after the power source is recovered, the processing which was being performed at the time of power failure. A memory cell MC can store two independent data sets; DRAM data (volatile data) and FeRAM data (non-volatile data). Thus, the number of memory cells can be reduced to a half. Also, the DRAM data to be used in the next operation of the two data sets which have been read out for the previous operation are temporarily held in a hold circuitof an operation unit OU and then written back into the memory cell MC in a non-volatile manner as new FeRAM data for preparation of the next operation. Thus, even when the power source is shut down by an unexpected trouble, the data necessary for the next operation are not lost.

Memory device with function to perform operation, and method of performing operation and storage

A switch circuit that is simple in constitution and capable of reliably controlling a switch cell is provided. Since the gate terminal Gof a transistor Min a switch cell SC is connected only to the terminalof a transistor Mwhen the transistor Mis set to off, the moving path of the charge accumulated at the gate Gof the transistor Mis shut off. Consequently, even if the transistor Mis set to an on state and immediately set back to an off state, the transistor Mremains for some period of time in an on or off state corresponding to the switching data given through a bit line BL. It is possible to cause the transistor Mto remain in an on or off state for a specified period of time without disposing a specific circuit for temporary storing the switching data.

It is an object of the present invention to provide a memory device with processing function using less transistors, and capable of operating with simple operation and allows its operation with less trouble. Each of W cells 34 includes a ferroelectric capacitor CF. One end 40 of the ferroelectric capacitor CF is connected to one of data lines D through a transistor T1. The one end 40 of the ferroelectric capacitor CF is connected to an inner data line MW through a transistor T2. The structure of the Q cells 36 is almost the same as that of the W cells 34. Both readout/writing operations of data from the outside of the device are performed by using the data line D. Data read out from both the W cell 34 and the Q cell 36 is sent to the adder 28 and added thereby, and the resultant data of the addition is written to the Q cell 36 through a buffer circuit 32. The memory device with processing function can be realized with a simple structure by using ferroelectric capacitors CF.

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Uji, Japan

Hiroshi Nozawa