Sumitomo Electric Industries, Limited

Hiroshi Notsu

Hisato Michikoshi

Noriyuki Hirakata

Takahiro Sugimura

A semiconductor device includes a semiconductor chip made of material containing silicon carbide, a base plate including a plate-shaped insulating body and metal layers disposed on opposite faces thereof, and a bonding material bonding the semiconductor chip on one face of the base plate, wherein the bonding material is made of a metal material whose post-bonding melting point is greater than or equal to 773&#xb0; C., wherein a thickness of the bonding material is less than or equal to 50 micrometers, wherein a thickness of the base plate is greater than or equal to 500 micrometers, and wherein with a thickness of the insulating body being denoted as t, and a thickness of each of the metal layers being denoted as t, a value of t/tis greater than or equal to 4.3.

Semiconductor device

Inexpensive production is achieved while avoiding the degradation of electrical performance caused by the lowering of heat dissipation. The base plateused here has a linear expansion coefficient of 2 to 10 ppm/K, which differs from the linear expansion coefficient of the semiconductor chipby an absolute value of 7 ppm/K or smaller. The bonding layeris formed such that the thickness b thereof is 50 micrometers or smaller, which is thinner than the thickness c of the semiconductor chip. Since the thickness b of the bonding layeris thinner than the thickness c of the semiconductor chip, the bonding layerupon the heating of the semiconductor chipexhibits thermal expansion that is of relatively small significance, and thus follows the expansion and contraction of the base plate. Since the linear expansion coefficient of the base plateis set close to that of the semiconductor chip, a displacement occurring between the base plateand the semiconductor chipin response to a temperature change is relatively small.

Semiconductor device and method of making semiconductor device

A semiconductor device includes at least one semiconductor chip, a gate wiring connected to the at least one semiconductor chip, a first wiring connected to the at least one semiconductor chip, and a second wiring connected to the at least one semiconductor chip. The first and second wirings extend along the gate wiring. The first wiring is arranged between the gate wiring and second wiring. The first wiring is the wiring closest to the gate wiring. A first part of the gate wiring opposing the first wiring is shorter than a second part of the gate wiring opposing the second wiring.

Semiconductor device including a gate wiring connected to at least one semiconductor chip

A semiconductor device includes a semiconductor chip, a die pad having a chip mount surface for mounting the semiconductor chip, and an electrode terminal for connecting with the semiconductor chip through first and second wirings. The electrode terminal has a first surface including a connection point with the first wiring and a second surface including a connection point with the second wiring. The connection point with the first wiring is located at a first height from a reference plane extending from the chip mount surface. The connection point with the second wiring is located at a second height different from the first height from the reference plane.

Growing community of inventors

Ibaraki, Japan

Hiroshi Notsu