Fujitsu Corporation

Fujitsu Semiconductor Limited

Socionext Inc.

Hiroshi Naritomi

Hayato Isobe

Osamu Kobayashi

Kazuya Taniguchi

Kunihiro Ohara

Yukisato Miyazaki

Masayuki Takeshige

Sumitaka Hibino

Hiroshi Fukuda

Teruyoshi Kondo

A power supply voltage control circuit device includes a power supply control circuit, a memory, and an arithmetic processing circuit. The power supply control circuit is configured to control a power supply voltage to be applied to a target circuit, and the memory is configured to store a first processing result when the target circuit is operated by setting the power supply voltage to a first voltage and a second processing result when the target circuit is operated by setting the power supply voltage to a second voltage different from the first voltage. The arithmetic processing circuit is configured to perform verify by reading the first processing result and the second processing result from the memory and output a result of the verify to the power supply control circuit, and wherein the power supply control circuit controls the power supply voltage based on the result of the verify.

Power supply voltage control circuit device and power supply voltage control method

A data recovery circuit for recovering data from a parity error without entirely rewriting the data. A write circuit is connected to memory regions including an actual data region and a copy region. A first parity generation circuit writes actual data with even parity to the actual data region. A second parity generation circuit writes backup data of the actual data with odd parity to the copy region. A read circuit reads data from the actual data region and the copy region. An even parity checker detects a parity error in the actual data based on the data read from the actual data region. An odd parity checker checks whether the data read from the copy region is backup data.

Data recovery circuit

A processor for performing calculations based on an instruction code, the number of bits of which is not an integer multiple of a byte. The instruction code is divided into higher order bits and lower order bits. The number of the lower order bits is an integer multiple of one byte. A memory stores the lower order bits in a lower order bit storage section and the higher order bits in a higher order bit storage section. The lower order bits and the corresponding higher order bits are read from the memory in the same cycle when generating the instruction code.

Method and apparatus for compactly storing instruction codes

An output circuit that prevents the flow of a leakage current from its output terminal to a power supply is able to accommodate voltage levels higher than the power supply voltage level. The output circuit includes a p-channel MOS transistor connected between the output terminal and a high potential power supply. A first switch circuit is connected between the transistor and the high potential power supply. The first switch circuit selectively connects and disconnects a back-gate of the transistor and the high potential power supply in response to an external signal applied to the output terminal.

Output circuit for electronic devices

Growing community of inventors

Kasugai, Japan

Hiroshi Naritomi