Semiconductor Technology Academic Research Center

Fuji Electric Co., Ltd.

Kyushu University

Hiroshi Nakashima

Ichiro Mizushima

Masanobu Miyao

Hitoshi Sumida

Masaki Yoshimaru

Taizoh Sadoh

Haigui Yang

A method of manufacturing a semiconductor device according to the invention includes the step Sof cleaning the silicon carbide substratesurface, the step Sof bringing a material gas into a plasma and irradiating the atoms contained in the material gas to silicon carbide substratefor growing silicon nitride filmon silicon carbide substrate, the step Sof depositing silicon oxide filmon silicon nitride filmby the ECR plasma CVD method, and the step Sof annealing silicon carbide substrateincluding silicon nitride filmand silicon oxide filmformed thereon in a nitrogen atmosphere. By the method of manufacturing a semiconductor device according to the invention, a semiconductor device that exhibits excellent interface properties including an interface state density and a flat band voltage is obtained.

Method of manufacturing semiconductor device

At least first and second SiGe(0&#x2266;x&#x2266;1) layers are formed on an insulating film. At least first and second material layers are formed correspondingly to the at least first and second SiGe(0&#x2266;x&#x2266;1) layers. A lattice constant of the first SiGe(0&#x2266;x&#x2266;1) layer is matched with a lattice constant of the first material layer. A lattice constant of the second SiGe(0&#x2266;x&#x2266;1) layer is matched with a lattice constant of the second material layer.

Semiconductor device including a plurality of different functional elements and method of manufacturing the same

There is provided a simulation method of instruction scheduling comprising detecting a loop from an instruction sequence to be simulated, registering an instruction scheduling target instruction sequence in a loop detection state, comparing a current scheduling target instruction sequence with the registered scheduling target instruction sequence for each loop cycle, and skipping, when the current scheduling target instruction sequence matches the registered scheduling target instruction sequence, scheduling of that scheduling target instruction sequence, and newly registering, when the two instruction sequences do not match, the current scheduling target instruction sequence and executing scheduling.

Simulation method and simulation system of instruction scheduling

Growing community of inventors

Fukuoka, Japan

Hiroshi Nakashima