Fujitsu Corporation

Nec Corporation

Nippon Telegraph and Telephone Corporation

Hiroshi Nakaide

Fumihiko Saito

Satoshi Takeda

Shinji Hiyama

Takahiro Hosokawa

Akio Morimoto

Shinzi Hiyama

Toshiaki Hayashi

Hiroyuki Kaneko

Hiroshi Takeo

Michinobu Ohhata

Masanori Kajiwara

Hiroshi Yamasaki

Takao Moriya

Koji Ikuta

Noriaki Ohuchi

Katsuhiko Nakamoto

Ikuo Washiyama

Toshinari Kunieda

Kensaburo Namba

Masashi Ohba

There are disclosed a mounting information-collecting device which is capable of collecting mounting information concerning mounted statuses of circuit boards with high accuracy and efficiency, as well as a connector and a mounting information-collecting method therefor. A light-emitting device emits an optical signal. A plurality of optical signal-processing elements each apply processing to the optical signal in a manner unique to a corresponding one of the circuit boards to thereby generate a processed optical signal. A mounting information-collecting device receives the processed optical signal and detects whether or not the processing has been applied, to thereby collect the mounting information.

Mounting information-collecting device, connector, and mounting information-collecting method

A control method and apparatus for the examination of multiport RAM(s) connected between a CPU on a CPU side and a hardware circuit on a hardware circuit side. The method and apparatus are for use in a device comprising a single RAM or more. For instance, the device may have a first RAM and a second RAM having ports on CPU and a hardware circuit side of the RAMs. Each one port on the CPU side is connected to a CPU. The method and apparatus examine the ports on the hardware circuit as well as the CPU side ports. The method may comprise steps of reading data stored in the first RAM from a port on the hardware circuit of the first RAM and writing the data in the second RAM from the port on the hardware circuit side of the second RAM using a RAM examination controller. The data read from the one port of the first RAM on the CPU side of the RAMs is compared with the data from the other port of the second RAM on the CPU side of the RAMs. The operation of ports of the first RAM and the second RAM on the hardware circuit side of the RAMs is examined.

Controlling method and apparatus for examination of multiport RAM(s)

A time switch control system having a cross-connect function is used for digital time-division. Multiplex communications permit desired channel settings and reduce power consumption. Identifying circuits identify which time-slot signals are to be retained by an input signal retaining memory, and output identification information to the retention memory, and to a retention memory controller. The retention memory controller stores therein the identification information from the identifying circuits, then reads out the identification information, and controls the input signal retaining memory in accordance with the contents of the identification information. Only the specified time-slot signals are stored and retained by the input signal retaining memory, thereby reducing power requirements. Exchange/output circuits exchange the time-slot signals stored in the input signal retaining memory in accordance with channel setting information, and output the exchanged signals.

Time-slot switching system identifying and storing only time-slot

At a CRC transmission side of a cross connect equipment, a CRC operation is applied to received channel data of each channel independently and sequentially in every sub frame having the same number of channels, series of which sub frames set up a main frame. The resultant CRC code of each channel obtained in a preceding sub frame is coupled to the received channel data of the corresponding channel to apply the same CRC operation to the thus received channel data, thereby the accumulated result of each channel is added in the last sub frame. At a CRC reception side, a cyclic CRC operation similar to that achieved at the CRC transmission side is applied to an outgoing channel data provided with the resultant CRC codes for each channel to obtain CRC results. During the cyclic CRC operation, a CRC error that once occurs is held during the main frame.

Channel data CRC systems for use with cross connect equipment

A multi-port time switch element for cross-connecting an n-channel multiplexed data includes m input ports for receiving m n-channel multiplexed data, a memory part for alternately writing and reading the n-channel multiplexed data, m selectors for writing and reading the n-channel multiplexed data so that each of the m selectors receives m.times.n data read from the memory part and selects one of the m.times.n data n times in an arbitrary sequence to output an n-channel multiplexed data, and m output ports for outputting the m n-channel multiplexed data read from the m selectors.

Multi-port time switch element

A clock distribution system includes a clock generation and distribution part for generating a clock signal and distributing the generated clock signal to a plurality of destinations, slots in each of which a clock reception unit can be detachably mounted, and a plurality of transmission lines coupling the clock generation and distribution part to the slots. Each slot includes a circuit for generating a mount state signal which indicates whether or not the slot is mounted with a clock reception unit, and for supplying the mount state signal to the clock generation and distribution part via a transmission line. This mount state signal has a first state when no clock receiving unit is mounted in the slot and has a second state when a clock receiving unit is mounted in the slot. The clock generation and distribution part includes a circuit for receiving the mount state signal from each slot and for transmitting via the transmission line the clock signal to each slot from which a mount state signal having the second state is received.

Clock distribution system

A digital signal transmission system includes a synchronization pattern detection circuit for detecting a synchronization pattern in response to a received transmitted digital signal, a pseudo synchronization detection circuit for detecting a pseudo synchronization pattern in the form of cyclic redundancy code in response to a received transmitted digital signal, and a synchronization protection circuit for counting the synchronization pattern detection signals produced when synchronization patterns are detected in response to a synchronization pattern detection signal from the synchronization pattern detection circuit. The synchronization protection circuit includes a main synchronization counter circuit and an auxiliary synchronization counter circuit. The count of protection steps for the confirmation of synchronization recovery of the auxiliary synchronization counter circuit in accordance with synchronization or asynchronization of the main synchronization counter circuit is variable.

Digital signal transmission system having frame synchronization operation

Growing community of inventors

Kawasaki, Japan

Hiroshi Nakaide