Hitachi, Ltd.

Renesas Electronics Corporation

Hiroshi Nakagoe

Yasushi Nagai

Shigeki Taira

Norio Suzuki

Makoto Kayashima

Hiromi Isokawa

Shinichi Tsunoo

Akira Yamamoto

Takatoshi Kato

Masanori Takada

Yoshihiro Yoshii

Tomotada Naito

Nobuaki Onodera

Example implementations described herein are directed to systems and methods to create authorization rules and configurations automatically for each microservice, each of which rules are built from the front-end use case. The example implementations involve a public facing environment on a public cloud system, and a test environment deployed on a private cloud system that is isolated from the public cloud system that mirrors the public cloud system functionality for testing deployment of applications.

System and method of microservice-based application deployment with automating authorization configuration

Example implementations are directed to a system and method to reduce deployment cost of data analytics application by designing both an application deployment plan and data integration plan, implementing the plans into an application template automatically and deploying application components and data in accordance with the desired implementation. Through example implementations, the need for separate terminals for a data engineer and an application engineer can be eliminated.

System and method of orchestration with data integration

A storage system selects from a plurality of physical areas constituting a physical address space as copy source physical areas, one or more non-additionally recordable physical areas each including a fragmented free area, and also selects a recordable physical area as a copy destination physical area. The storage system then writes one or more pieces of live data from the selected one or more copy source physical areas to the free area of the selected copy destination physical area on a per-strip or per-stripe basis, sequentially from the beginning of the free area. If the size of the write target data is such that it is not possible to write the write target data to the free area on a per-strip or per-stripe basis, then the storage system pads the write target data, and writes the padded write target data to the free area on a per-strip or per-stripe basis.

Storage system and storage control method

A service performance, such as a responsiveness and throughput, is improved in a distributed system including system components distributed over a plurality of regions. A route resolution system, is coupled to a distributed system including a plurality of components which configure the system and which are distributed over a plurality of regions, converts a measured value of a processing performance between the components into a standard value independent from network performance information, derives, upon receiving a route inquiry request from a component to which a request from a client terminal has been forwarded, a plurality of routes being coupled the plurality of the components for processing the request, calculates an estimated value of performance information required for processing the request, for each of the plurality of routes based on the standard value of the same request, and determines an optimal route based on the calculated estimated value.

Route resolution system and route resolution method

The present invention efficiently displays in a tree structure form a file operation history. A file storage identifier, an operation identifier, and a count are stored as additional meta-information in an alternate data stream with respect to each file stored in a client terminal file system. The operation identifier manages a number of operations (operation generations). The count manages copy frequencies. This meta-information is also sent to a management apparatus, and used for displaying the file operation history in a tree structure form.

Computer system management method and client computer

In the configuration performing a data processing by a hardware processing circuit (accelerator), to provide a technology capable of improving a poorness of processing efficiency by multiple accesses to the data, the following solving means are provided. A network data processing accelerator of the present network data processing apparatus comprises processing units corresponding to each processing of an encryption/decryption, a message authentication, and a checksum, and in the data processing including a combination of each processing, accesses for the same data of the memory and the like through a bus I/F unit and the like is collected together into one time, and a pipeline processing is performed using the least common multiple of the data processing unit of each processing.

Data processing apparatus

The content of operations is identified and an alert is generated to an operation having a high risk of information leakage. An agent monitors, for example, operations performed with respect to a dialogue displayed on a client PC. If a file is selected by an operation performed with respect to the displayed dialogue, the agent assigns an identifier indicating a source for the file to the file. If the file is sent as an attached file, the agent identifies an output destination for the attached file as well as the source for the attached file; and if the output destination for the attached file is an external Web server and the source for the attached file is a mail server, the agent generates an alert by determining that an unauthorized operation has been executed; and then sends the generated alert to a management server.

Unauthorized operation detection system and unauthorized operation detection method

A client computer detects a user operation for transmitting data to a server or a storage device, determines whether the detected user operation is a fraudulent manipulation, and, if the determination is a positive result, performs security processing which is processing related to security of data to be transmitted. If the data is data within a group to which the user belongs and a destination of the data is a server or a storage device outside the group, the determination is a positive result.

Fraudulent manipulation detection method and computer for detecting fraudulent manipulation

This arithmetic logical unit outputs data to be used in checking the final result of an AES unit that encrypts a plain text block into an encrypted text block based on AES operation, and includes an arithmetic unit for computing parity data created based on XOR operation from an encryption key to be used as a key during AES encryption, parity data created based on XOR operation from a plain text block, and an AES operation halfway result output from the AES unit, and outputting a value that is equivalent to parity data created based on XOR operation from the final result of the AES unit.

Arithmetic logical unit, computation method and computer system

The DMA controller includes a peripheral device read unit to read states of peripheral devices, a state comparator, a transfer unit, a register, and a peripheral device write unit to write data in the peripheral devices according to the contents in the register when the DMA transfer is executed, an interrupt select unit selects one of plural interrupt signals to determine whether the peripheral device read unit, the state comparator and the transfer unit are at a timing to execute operations. Based on these operations the state comparator determines whether to start the DMA transfer, and the transfer unit executes data transfer between the peripheral devices.

DMA controller

A DMA controller achieving real-time control of a DMA transfer relating to periodically operated peripheral devices at a low cost and with low power consumption. A typical embodiment of the invention is a DMA controller having: a counter for counting time; a counter comparator comparing a value of the counter and a counter value indicating an expected time of a DMA transfer; a peripheral device read unit reading a register of the peripheral device to acquire a state of a peripheral device by; and a state comparator comparing a value of the register read by the peripheral device read unit and a start condition of the DMA transfer, in which, with being triggered by establishment of a comparison result by the counter comparator, in accordance with a specified order, a processing of updating the counter value indicating the expected time of a DMA transfer to a value indicating a next expected time, a read of the register of the peripheral device by the peripheral device read unit, a comparison by the state comparator, and a DMA transfer on the condition that the comparison result by the state comparator is established are executed.

An operational circuit for performing an operation of an arbitrary number of input data pieces by using a DMA transfer according to a descriptor control and output results. The arbitrary number of input data pieces are divided into a plurality of pieces to perform an operation processing without performing the operation of the arbitrary number of input data pieces at a time. The operational circuit once stores an intermediate result for each of the divided operations in an external storage device, performs an operation processing read with an intermediate result in the next operation processing, and obtains a final result by repeating these operation processings. The operation is performed at a cyclic unit of processing corresponding to the number of address registers provided in the operational circuit.

Growing community of inventors

Yokohama, Japan

Hiroshi Nakagoe