National Institute of Advanced Industrial Science and Technology

Agency of Industrial Science and Technology

Pi R&d Co., Ltd.

Kiyota Manufacturing Co.

Kiyoto Manufacturing Co.

Ministry of International Trade & Industry

Futaba Denshi Kogyo K.k.

Agency of Industrial Science and Technology Ministry of International

Kanto Kagaku Kabushiki Kaisha

Shinwa Corp. Ltd.

Tss Corporation

Kabushiki Kaisha Mikuni Kogyo

Hiroshi Nakagawa

Masahiro Aoyagi

Katsuya Kikuchi

Yoshikuni Okada

Kazuhiko Tokoro

Shigeo Kiyota

Yasuhiro Yamaji

Hiroyuki Fujita

Tokihiko Yokoshima

Hiroshi Itatani

Sigemasa Segawa

Itaru Kurosawa

Kenichi Kobayashi

Shigeo Itoh

Teruo Watanabe

Masaru Kato

Kazuhiko Tsuburaya

Ryota Iwai

Tomoaki Tokuhisa

Masaaki Maezawa

Takashi Nanya

Yoshihiko Hirata

Susumu Takada

Ying Ying Lim

Yoshihiro Gomi

Hirotaka Oosato

Shouichi Imai

Masaru Hashino

Yoshio Kameda

Shoichi Imai

The purpose of the present invention is to provide an electronic circuit connection method and an electronic circuit capable of improving the reliability of electrical connection. A connection method for an electronic circuitincludes: a process of forming a first metal bumpsand a second metal bump, each of which has a cone shape; and a process of joining a first electrode padand a third electrode padby the first metal bumpand joining a second electrode padand a fourth electrode padby the second metal bump, wherein at least one region of between a first regionand a second regionin a first connection surfaceand between a third regionand a fourth regionin a second connection surfacehas a step, and the first metal bumpand the second metal bumphave different heights so as to correct a height Hof the step

Electronic circuit connection method and electronic circuit

An electroless gold plating solution with which one or more openings formed in a resist overlying a substrate can be filled in a short time, the openings having a width on the order of micrometer, in particular, 100 &#x3bc;m or smaller, in terms of the width of the exposed substrate area, and having a height of 3 &#x3bc;m or larger. The electroless gold plating solution contains a deposition accelerator for deposition in fine areas, and a microfine pattern of 100 &#x3bc;m or finer is formed therefrom.

Electroless gold plating solution for forming fine gold structure, method of forming fine gold structure using same, and fine gold structure formed using same

A method of making a contact probe including a step of making a first printed wiring board having a signal electrode and a ground electrode used as a contact part of the contact probe with respect to a measuring object, in which the signal electrode and ground electrode are formed of a metal wiring pattern, and making a second printed wiring board with a coaxial line structure having a shield electrode which encloses a signal line and the surroundings of the signal line through an insulating layer. The signal electrode of the first printed wiring board and the signal line of the second printed wiring board are electrically connected together, and the ground electrode of the first printed wiring board and the shield electrode of the second printed wiring board are electrically connected together.

Method of making contact probe

An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.

Electrode connection structure of semiconductor chip, conductive member, and semiconductor device and method for manufacturing the same

To provide a contact probe which can easily be connected with a measurement apparatus electrically, can measure a high speed and high frequency signal with a fine pitch easily and correctly, and can easily cope with signal measurement for a plurality of channels, and a method of making the contact probe. It includes a first printed wiring boardhaving a signal electrodeand a ground electrodeused as a contact part with respect to a measuring object, in which the signal electrodeand ground electrodeare formed of a metal wiring pattern on a substrate, and a second printed wiring boardwith a coaxial line structure having shield electrodeswhich enclose a signal lineand the surroundings of the signal linethrough an insulating layer. The signal electrodeof the first printed wiring boardand the signal lineof the second printed wiring boardare electrically connected together, and the ground electrodeof the first printed wiring boardand the shield electrodesof the second printed wiring boardare electrically connected together.

Contact probe and method of making the same

An interposer having multi-layer fine wiring structure which comprises an insulating layer made of photosensitive polyimide which is photosensitive organic material and a wiring layer portion made of metal, such as copper, silver, gold, aluminum, palladium, indium, titanium, tantalum, and niobium, functions as wiring in an integrated circuit chip, wherein junctions between the integrated circuit chip and the interposer are formed by micron to submicron size fine connection metal pads or bumps which are formed on both the integrated circuit chip and the interposer.

Multi-layer fin wiring interposer fabrication process

The present invention provides a method of forming a micro metal bump, which is capable of stably and industrially forming a micro metal bump, by a gas deposition process, at a prescribed position of a metal part formed on one side surface of a substrate. The method comprises the steps of: forming a straight hole () in a mask layer () covering one side surface of a substrate () on which a wiring pattern () is formed, wherein a prescribed position of the wiring pattern () is exposed in a bottom surface of the straight hole and the straight hole has an inner wall perpendicular to the one side surface of the substrate () and a sharp top opening portion; providing a metal plate, whose area is larger than that of the substrate (), on the other side surface of the substrate () as a heat sink; placing the substrate () and the metal plate in a vacuum; forming a tapered metal bump () on the exposed surface of the wiring pattern (), which is exposed in the bottom surface of the straight hole (), by a gas deposition process, in which metal nanoparticles obtained by evaporating a metal are ejected from a nozzle together with a carrier gas so as to deposit on the prescribed position, with cooling the substrate () to a temperature lower than upper temperature limit of resin constituting the mask layer (), by the metal plate as the heat sink, so as to retain a configuration of the straight hole (); and removing the mask layer () from the one side surface of the substrate so as to complete the tapered metal bump () at the prescribed position of the wiring pattern ().

Method of forming micro metal bump

A system in-package test inspection apparatus for measuring and evaluating the high-speed/high frequency characteristic of a system in-package through an electrode pad in which I/O terminals are formed on one side of an LSI package containing metallic wiring internally and plural LSI chips are stacked in multiple layers on the other face while electric connection between the LSI chip and the LSI package and the electric connection between the LSI chips are implemented, the system in-package test inspection apparatus comprising: a printed wiring substrate to which the I/O terminals of the system in-package are connected to enable transmission of high speed and high frequency signals; LSI chip driving means for driving the LSI chip; a contact probe having a contact electrode and for transmitting a high frequency signal; evaluation signal generating means for supplying a high frequency evaluation signal to the contact probe; output signal detecting means for detecting an output signal of the system in-package through the printed wiring board; and analyzing means for analyzing a signal detected by the output signal detecting means, wherein by contacting the contact electrode of the contact probe with an electrode pad formed on the LSI chip, the evaluation signal is inputted to the LSI chip not through metallic wiring within the LSI package.

System in-package test inspection apparatus and test inspection method

A superconducting integrated circuit includes a substrate, a multilayer structure formed on the substrate and composed of a lower superconducting electrode, a tunnel barrier and an upper superconducting electrode sequentially joined together upward in the order mentioned, and an insulating layer perforated to form via holes to get electrical contacts with the lower and upper electrodes. The insulating layer is formed of a high-resolution, photosensitive, solvent-soluble, organic insulating material. The superconducting integrated circuit is produced by a method that includes the steps of depositing the multiplayer on the substrate, applying the insulating material to the front surface of the substrate inclusive of the multiplayer, forming the via holes in the insulating material by the lithographic technique at the prospective positions to get electrical contacts with the upper and lower electrodes, and laying wirings for connecting the upper and lower electrodes through the via holes.

Superconducting integrated circuit and method for fabrication thereof

There is provided a contact probe that is smaller than 50 &#x3bc;m in a pitch between a signal electrode and a ground electrode and can correctly conduct a high-speed high-frequency measurement, a measuring pad used for the contact probe, and a method of manufacturing the contact probe. The contact probe includes: a tip member having a signal electrodeand a ground electrodethat are put into contact with an object to be measured; and a coaxial cablehaving a coreelectrically connected to the signal electrodeand an outer covering conductor la electrically connected to the ground electrode, wherein the tip member is formed on a printed wiring board, and wherein the signal electrodeand the ground electrodeare constructed of fine coplanar strip lines formed on an insulating board

Contact probe, measuring pad used for the contact probe, and method of manufacturing the contact probe

There is provided a contact probe that is smaller than 50 &#x3bc;m in a pitch between a signal electrode and a ground electrode and can correctly conduct a high-speed high-frequency measurement, a measuring pad used for the contact probe, and a method of manufacturing the contact probe. The contact probe includes: a tip member having a signal electrodeand a ground electrodethat are put into contact with an object to be measured; and a coaxial cablehaving a coreelectrically connected to the signal electrodeand an outer covering conductorelectrically connected to the ground electrode, wherein the tip member is formed on a printed wiring board, and wherein the signal electrodeand the ground electrodeare constructed of fine coplanar strip lines formed on an insulating board

A field emission element including an electrode structure made of a thin film exhibiting increased adhesive strength. A thin film of niobium nitride (NbN) is formed on a glass substrate by sputtering or the like. The NbN film exhibits increased adhesive strength to a degree sufficient to prevent etching for formation of the film into electrodes from causing peeling of the film.

Vacuum airtight device having NbN electrode structure incorporated

An elementary cell uses single-flux-quanta as two-valued logic propagation signals and is effective for Constructing asynchronous superconducting logic circuits. The elementary cell comprises one OR circuit section and one AND circuit section. Input pulses applied to two input terminals of the elementary cell are split at signal splitting sections in the elementary cell and applied to both inputs of the OR circuit section and both inputs of the AND circuit section. The output of the OR circuit section is defined as the OR output of the elementary cell. A first arrival pulse memory section is provided in the AND circuit section and when one of two input pulses input to the two input terminals of the AND circuit section arrives before the other, this fact is recorded in the first arrival pulse memory section as logical '1'. When the other input pulse arrives while logical '1' is recorded in the first arrival pulse memory section, the AND circuit section produces an AND output which is defined as the AND output of the elementary cell. When a reset signal pulse is applied to a reset terminal, the first arrival pulse memory section is reset.

Elementary cell for constructing asynchronous superconducting logic

Growing community of inventors

Tsukuba, Japan

Hiroshi Nakagawa