Renesas Technology Corp.

Hitachi, Ltd.

Other

Hitachi Ulsi Systems Co., Ltd.

Renesas Electronics Corporation

Hiroshi Momiji

Naotaka Hashimoto

Hiromi Abe

Shinichi Fukada

Masayuki Suzuki

Masanori Kojima

Shuji Ikeda

Shinji Nishihara

Masayuki A Suzuki

A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

Method of fabricating semiconductor integrated circuit device

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and' a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt suicide, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Method of fabricating semiconductor device

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Method for fabricating semiconductor device

Method of fabricating semiconductor integrated circuit device with 99.99 wt% cobalt

A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and' a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Process for producing semiconductor integrated circuit device

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region ( ), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide , so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

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London, United Kingdom

Hiroshi Momiji