Mitsubishi Denki Kabushiki Kaisha

Hiroshi Mochizuki

Shigeru Harada

Hiroshi Adachi

Etsushi Adachi

Eisuke Tanaka

Hirozoh Kanegae

Kenji Kishibe

Masaaki Ikegami

Kimio Hagi

Junichi Arima

Koji Eguchi

Tamio Matsumura

Takeshi Noguchi

Reiji Tamaki

Kazuhito Matsukawa

Masanori Obata

Takemi Endoh

Akira Ohhisa

Akira Ohisa

Akira Ihisa

Kenji Saito

A process control method allowing an operator to readily confirm an order of operation processes includes steps of: reading magnetic data of a control card when the control card is inserted; transmitting completion data based on a lot number identified from read magnetic data to a host computer; receiving update data by the host computer; writing next process data in the received data as a visually recognizable image on the control card; and writing the next process data as a visually recognizable image based on process data identified by the read magnetic data when a predetermined time period passes without receiving update data.

Process control device and process control method using a medium with rewritable marking technique

A semiconductor integrated circuit structure includes a semiconductor substrate; an electronic element disposed in the substrate; a first electrically insulating layer disposed on the substrate and the electronic element; a first electrically conducting interconnection layer electrically connected to the electronic element and disposed at least partly on the first electrically insulating layer; a second electrically insulating layer disposed on the first electrically conducting interconnection layer; a second electrically conducting interconnection layer disposed on the second electrically insulating layer; and a through-hole penetrating the second electrically insulating layer to the first electrically conducting interconnection layer, part of the second interconnection layer being disposed within the through-hole and contacting the first electrically conducting interconnection layer wherein the first electrically conducting interconnection layer includes a current barrier including at least one opening in the first electrically conducting interconnection layer proximate the through-hole extending to the first electrically insulating layer and filled with part of the second electrically insulating layer, constraining current flowing between the first and second electrically conducting interconnection layers to flow around the current barrier. A method of making a semiconductor integrated circuit interconnection structure includes forming an active electronic element in a semiconductor substrate; forming a first electrically insulating layer on the electronic element and the semiconductor substrate; forming a first electrically conducting interconnection layer electrically connected to the electronic element, at least partially disposed on the first electrically insulating layer, and including at least one opening extending to the first electrically insulating layer; forming a second electrically insulating layer on the first electrically conducting interconnection layer and filling the opening, thereby forming a barrier to the flow of current in a region of the first electrically conducting interconnection layer; forming a throughhole extending through the second electrically insulating layer to the first electrically conducting interconnection layer proximate the opening; and depositing a second electrically conducting interconnection layer on the second electrically insulating layer and in the through-hole, electrically contacting the first electrically conducting interconnection layer.

Semiconductor integrated circuit interconnection structures and method

A semiconductor integrated circuit structure includes a semiconductor substrate; an electronic element disposed in the substrate; a first electrically insulating layer disposed on the substrate and the electronic element; a first electrically conducting interconnection layer electrically connected to the electronic element and disposed at least partly on the first electrically insulating layer; a second electrically insulating layer disposed on the first electrically conducting interconnection layer; a second electrically conducting interconnection layer disposed on the second electrically insulating layer; and a through-hole penetrating the second electrically insulating layer to the first electrically conducting interconnection layer, part of the second interconnection layer being disposed within the through-hole and contacting the first electrically conducting interconnection layer wherein the first electrically conducting interconnection layer includes a current barrier including at least one opening in the first electrically conducting interconnection layer proximate the through-hole extending to the first electrically insulating layer and filled with part of the second electrically insulating layer, constraining current flowing between the first and second electrically conducting interconnection layers to flow around the current barrier.

Semiconductor integrated circuit interconnection structures

The present invention is mainly characterized by providing an even surface of an interlayer insulating film for insulating and isolating an upper interconnection and a lower interconnection from each other. A lower interconnection layer is provided on a semiconductor substrate, having a pattern of stepped portions. A silicon type insulating film is provided on the semiconductor substrate so as to cover the lower interconnection layer. A silicon ladder resin film is filled in recessed portions of the surface of the silicon type insulating film for making even the surface of the silicon type insulating film. An upper interconnection layer electrically connected to the lower interconnection layer through a via hole is provided on the silicon type insulating film. The silicon ladder resin film has the structural formula: ##STR1## where R.sub.1 is at least one of a phenyl group and a lower alkyl group, R.sub.2 is at least one of a hydrogen atom and a lower alkyl group, and n is an integer of 20 to 1000.

Semiconductor device and manufacturing method thereof

A semiconductor device sealed with mold resin is disclosed. The device includes a semiconductor substrate having a main surface and an element formed on the main surface of the semiconductor substrate. A stress buffering film for protecting at least the element from stress of the mold resin is provided on the semiconductor substrate so as to cover at least the element. The entire semiconductor device is covered and sealed with mold resin. The stress buffering film is formed of organo-silicone ladder polymer having a hydroxyl group at its end. In the semiconductor device, water does not get into an interface of the stress buffering film and the underlying substrate, resulting in an enhancement of the moisture resistance of the semiconductor device.

Semiconductor device sealed with mold resin

The disclosed is a method of manufacturing a semiconductor device sealed with molding resin. An aluminum interconnection including an aluminum electrode pad is formed on a semiconductor substrate having an element. A silicone ladder polymer expressed by the following general formula is formed on the semiconductor substrate to cover the element. The silicone ladder polymer film is selectively etched by an aromatic organic solvent to expose the surface of the aluminum electrode pad. The temperature of the silicone ladder polymer film is elevated at a temperature elevating rate of 20.degree. C./min or more, and then, the silicone ladder polymer film is cooled at a cooling rate of 20.degree. C./min or more to form a cured stress buffering protective film for buffering a stress applied to the element. ##STR1## (in the formula, n is an integer which makes the weight-average molecular weight be in the range of 100,000 to 200,000.)

Method of manufacturing a semiconductor device sealed with molding resin

An improved interconnection structure and method for forming the interconnection in a semiconductor device having multilayered interconnection structure in which a contact hole for electrically connecting a first layer interconnection to a predetermined region of a semiconductor substrate and a through hole for electrically connecting a second layer interconnection to the first layer interconnection are formed in the regions overlapping with each other in planer layout. In the interconnection structure of the present invention, hillocks effective to compensate for the contact hole step are formed in the first layer interconnection only in the region of the contact hole of the first layer interconnection. In the method for forming the interconnection according to the present invention, a first layer interconnection is formed and a chemical conversion process is selectively performed to form a film which is more rigid than the first layer interconnection film on a predetermined region of the first layer interconnection film, and then a heat process is performed to generate hillocks only at the region of the contact hole of the first layer interconnection film. The second layer interconnection film is formed thereafter.

Semiconductor device and method for making the same

An apparatus for forming a thin film on a substrate has a first reaction chamber in which a thin film is formed by gaseous discharge and a second reaction chamber in which reactive atoms are generated. The first and second reaction chambers commuicate with one another through an orifice in the first reaction chamber. The first reaction chamber houses a device for generating a film on a substrate, and the second reaction chamber houses a device for generating reactive atoms. The orifice is disposed in the vicinity of both a film-forming region in the first reaction chamber and a reactive atom-generating region in the second reaction chamber so that reactive atoms from the second reaction chamber will pass through the orifice and enter the film-forming region in the first reaction chamber, combine with particles in the film-forming region to form a chemical compound, and accumulate on the substrate. In preferred embodiments, the reaction chambers are formed by a single housing having a partition which has an orifice therein and which divides the housing into two reaction chambers.

Growing community of inventors

Hyogo, Japan

Hiroshi Mochizuki