Hitachi, Ltd.

Hiroshi Mizuta

Kiyoo Itoh

Toshikazu Shimada

Kazuo Nakazato

Hideo Sunami

Ken Yamaguchi

Tatsuya Teshima

Toshiyuki Mine

Susumu Takahashi

Tomonori Tanoue

Toshihiko Sato

Haroon Ahmed

Chushirou Kusano

Kazuhito Tsukagoshi

Bruce William Alphenaar

A controllable conduction device in the form of a transistor comprises source and drain regionsbetween which extends a conduction path P for charge carriers, a gatefor controlling charge carrier flow along the conduction path and a multiple layer structureproviding a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Controllable conduction device with electrostatic barrier

A magnetoelectric device responsive to an applied magnetic field, e.g. for use as a reading head for data stored in magnetic storage media, comprises first and second ferromagnetic regions ( ) with a channel region ( ) between them, the ferromagnetic regions being configured so that charge carriers with a particular spin polarization which can pass through the first region, pass through the second region as a function of the relative orientations of magnetization of the ferromagnetic regions produced by the applied magnetic field such that the device exhibits a conductivity as a function of the strength of the applied field. The channel region ( ) includes a nanotube ( ) which may be formed of carbon, configured to provide a quasi-one-dimensional channel to cause charge carriers which pass through the first ferromagnetic region to maintain their spin polarization as they pass towards the second ferromagnetic region. In an alternative embodiment a deposited carbon layer ( ) is used in the channel region.

Magnetoelectric device

Semiconductor memory device and manufacturing method

A memory device includes a memory node ( ) to which charge is written through a tunnel barrier configuration ( ) from a control electrode ( ). The stored charge effects the conductivity of a source/drain path ( ) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers ( ) of polysilicon of 3 nm thickness and layers ( ) of Si N of 1 nm thickness, overlying polycrystalline layer of silicon ( ) which forms the memory node. Alternative barrier configurations ( ) are described, including a Schottky barrier configuration, and conductive nanometer scale conductive islands ( ), which act as the memory node, distributed in an electrically insulating matrix.

Memory device

Semiconductor memory device and manufacturing method thereof

A controllable conduction device in the form of a transistor comprises source and drain regions,between which extends a conduction path P for charge carriers, a gate,for controlling charge carrier flow along the conduction path and a multiple layer structure,providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Controllable conduction device

Semiconductor logic element and apparatus using thereof

A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si.sub.3 N.sub.4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometre scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.

Memory device with improved charge storage barrier structure

A semiconductor device is disclosed, which includes a multiple negative differential resistance element having negative differential resistance characteristics at at least two places in the current-voltage characteristics, and which is suitable for constructing a neural network having a high density integration and a high reliability.

Electric circuit using multiple differential negative resistance

A resonant tunneling device includes a superlattice layer which includes an interlaminated structure of three semiconductor layers each having a narrow energy bandgap and serving as a quantum well layer and four semiconductor layers each having a wide energy bandgap and serving as a barrier layer and in which three quantum levels are formed in the quantum well layers. A resonant tunneling phenomenon produced between the quantum levels provides peak current values which are substantially equal to each other, peak voltages which can be set independently from each other, and peak-to-valley (P/V) ratios which are high, thereby realizing a resonant tunneling device which has an excellent performance as a three state logic element for a logic circuit. By increasing the number of quantum well layers and the number of barrier layers, a logic element of four or more states can be realized for a logic circuit.

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Tokyo, Japan

Hiroshi Mizuta