Mitsubishi Denki Kabushiki Kaisha

Nintendo Co., Ltd.

Optical Measurement Technology Development Co., Ltd.

Mitsubishi Denki Kabushiki Denki

Hiroshi Miyamoto

Michihiro Yamada

Shigeru Mori

Shigeru Kikuda

Makoto Suwa

Yoshikazu Morooka

Tadato Yamagata

Kiyohiro Furutani

Mitsuya Kinoshita

Kazutami Arimoto

Koichiro Mashiko

Toshifumi Kobayashi

Tetsuya Aono

Hiroshi Okuda

Tadaaki Yamauchi

Hiroshi Koizumi

Yasuhiko Tsukikawa

Kenichi Yasuda

Hideto Iwaoka

Kazutoshi Hirayama

Yoshiaki Onishi

Nobuo Matsumiya

Makiko Aoki

Mizuki Murata

Shunsuke Matsushita

Nobuya Ohashi

Kazuhisa Watanabe

Yuichi Mizobe

A non-limiting example game apparatus includes a first LCD and a second LCD, a touch panel is provided on the second LCD. A pre-hitting operation screen is displayed on the second LCD, and a mark for designating a target landing point is displayed in this screen. A player designates a desired target landing point by moving the mark by a touch operation. A target shot power value for causing a ball to arrive the designated target landing point is calculated with using parameters set for a club that is currently selected. However, when the designated target landing point exceeds a position that the ball is hit using the club under selection with a maximum power value, the mark is moved to the position concerned and the maximum power value is set as a target shot power value.

Golf game apparatus, storage medium, golf game system and golf game control method

A method and apparatus for affixing a functional film on a panel surface having a curvature in three dimensional directions with at least one pushing roller. A pressing roller which is elastic has a shaft inside the roller. The shaft has a varied diameter of concave curvature with the largest portions at the ends of the shaft. The inner portion of the elastic roller is separated from the shaft by a clearance which is greater in the middle of the shaft. When the roller is pressed upon a three dimensional panel, the elastic roller is deformed into the clearance area and against the shaft. This permits even pressure to be applied across the panel. In a second embodiment, a main pushing roller unit may travel along the direction while pushing the functional film against the panel surface, followed by the two follow-up displacement pushing roller units which are displayed in response to the travel of the main pushing roller unit while pushing the functional film against the panel surface.

Device for manufacturing panel with functional film

A .phi..sub.C generation circuit provides a column address buffer control signal to a column address buffer so that the column address buffer maintains a latch operation during the operation period of a differential amplifier. The column address buffer responds to a column address buffer control signal to latch an input address signal for providing a column address signal to a .phi..sub.D and PAE generation circuit. The .phi..sub.D and PAE generation circuit provides a differential amplifier activation signal to the differential amplifier according to a column address signal and a column access activation signal. The differential amplifier responds to a differential amplifier activation signal for amplifying data applied from a data input and output line to provide the same to a selector via a readout data line.

Semiconductor memory device that can read out data at high speed

A DRAM includes a package, a semiconductor chip housed in the package, and a plurality of leads each disposed from the outside of the package over the periphery of the semiconductor chip. The power supply potential is applied to some of the leads. Corresponding to one power supply lead, one power supply pad and one selection pad are formed. Corresponding to another power supply lead, another power supply pad and another selection pad are formed. Each of these two selection pads is connected or not connected to the corresponding power supply lead by bonding. As a result, one of four word configurations is selected. Since these two selection pads are disposed in the vicinity of the corresponding power supply leads, respectively, the number of times of bonding to one power supply lead is reduced.

Semiconductor integrated circuit device having improvement arrangement

In a memory cell array, data lines are formed into a hierarchical arrangement of sub data lines provided for every block and a main data line common to each block, and a sub data line selected by a column address among sub data lines belonging a block which are simultaneously selected by a row address is connected to a bit line. Accordingly, the sub data line length is reduced, which reduces floating capacitance, reading and writing operations can be conducted at a high speed, and sub data lines can be selectively operated. In addition, power required for charging the sub data lines can be reduced, and entire power consumption by the semiconductor memory device can be reduced as well.

Semiconductor memory device permitting high speed data transfer and high

A semiconductor memory device includes a plurality of memory blocks, i main row or column select lines extending over the plurality of memory blocks, and a decoder for selecting one of the main row or column select lines in accordance with an applied address signal. The decoder includes i outputs. Each of the memory blocks includes a plurality of memory cells arranged in rows and columns and at least (i+1) sub row or column select lines each for selecting one row or one column of memory cells. A shift redundancy circuit is provided for each of the memory blocks, for connecting the main row or column select line and the sub row or column select line. The shift redundancy circuit includes a switch circuit for connecting one main row or column select line to one of the plurality of adjacent sub row or column select lines, and a circuit for setting a connection path of the switch circuit. The shift redundancy circuit connects successively adjacent sub row or column select lines to main row or column select lines in one to one correspondence except a defective sub row or column select line associated with a defective bit.

Redundancy circuit for repairing defective bits in semiconductor memory

Read data supplied from one of a plurality of differential amplifier circuits is transmitted to a read data bus driver circuit via one of a plurality of CMOS transfer gates and a data latch circuit. The potential of read data bus pair is forcedly set to a low level in response to a control signal until the read data is transmitted to the read data bus driver circuit. Thereafter, the read data bus driver circuit drives the read data bus pair in accordance with the transmitted read data. Thereby, a speed of the address access operation can be increased without outputting invalid data.

Semiconductor memory device providing external output data signal in

A chip is divided into at least four regions of two rows and two columns. In each region, memory array blocks are provided between corresponding first control circuits disposed in the column direction at a constant pitch. A column decoder is disposed adjacent to the first control circuit. Second control circuits are disposed corresponding to the first control circuits. The second control circuits excluding the second control circuit on the column decoder side are formed in the same pattern.

Semiconductor memory device suitable for high integration

Disclosed is a DRAM including a power-on reset signal generating circuit for outputting a voltage of a predetermined level for a definite period by utilizing a rise of an external supply voltage, and a supply voltage conversion circuit for lowering the external supply voltage to a constant voltage. In this DRAM, the power-on reset signal generating circuit is driven by the external supply voltage not an output voltage of the supply voltage conversion circuit. The output voltage of the supply voltage conversion circuit is applied to various internal circuits including smaller-scale MOS transistors, to drive these internal circuits. Since the supply voltage conversion circuit often includes circuit components with a large time constant in order to decrease power consumption, the output voltage of the supply voltage conversion circuit rises rather slowly than the external supply voltage. However, the power-on reset signal generating circuit receives the external supply voltage as a driving voltage and hence immediately outputs a normal one-shot pulse in response to the supply of power to the DRAM.

Semiconductor integrated circuit apparatus including supply voltage

A semiconductor memory device includes a memory array. The bit line pairs of the odd number order in the memory array belong to a first group, and the bit line pairs of the even number order belong to a second group. A first amplifier is connected to each bit line pair. Corresponding to the first group, write buses read buses and a read/test circuit are provided. Corresponding to the second group, write buses read buses and a read/test circuit are provided. A column decoder selects a plurality of bit line pairs simultaneously at the time of testing. At the time of testing, each of the read/test circuits compares data read out from the plurality of bit line pairs belonging to the corresponding group with a given expected data for providing the comparison result.

Semiconductor memory device comprising a test circuit and a method of

A plurality of sub chips are formed on a chip. An input/output buffer region is arranged around the plurality of sub chips. Each sub chip includes a sub chip control circuit region and a plurality of memory cell array blocks. Each memory cell array block includes a memory cell array region, a row decoder and control circuit region, a sense amplifier region and an input/output latch region.

Semiconductor integrated circuit device including a plurality of cell

A dynamic random access memory (DRAM) includes a selection circuit for selecting the voltages used for aging. The selection circuit operates responsive to external control signals. When a source voltage (Vcc) is selected, the voltage (Vcc) is supplied to one electrode of a memory cell via a circuit 73 and a transmission gate while a ground potential (Vss) is supplied to the other electrode via a bit line and a transistor. Conversely, when the ground potential (Vss) is selected, an inverted voltage is applied across the two electrodes. In this manner, the insulating properties of an insulator interposed between the two electrodes can be checked more reliably during aging.

Circuit for applying selected voltages to dynamic random access memory

Column repairing circuits 7a, 7b for repairing a DRAM in which there are defective memory cells in two columns are disclosed. The connection state of switching elements or circuits 51-5n, 61-6n, 71-7 (n+1), 81-8 (n+1) is determined as illustrated by appropriately disconnecting fuses in fuse links provided respectively in circuits 7a, 7b. Accordingly, column selecting lines Y2a and Y (n+1) b in memory array blocks 891a, 891b are not activated. The two repairing circuits 7a, 7b are provided spaced apart from each other on a semiconductor substrate, so that excessive concentration of fuse elements and switching elements or circuits is prevented.

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Hyogo, Japan

Hiroshi Miyamoto