Fujitsu Corporation

Fujitsu Semiconductor Limited

Hiroshi Miyake

Hiroshi Miyazaki

Yasuhiro Aso

Satoshi Kakuma

Shuji Yoshimura

Noriyuki Tokuhiro

Tadao Aikawa

Yoshihiro Uchida

Naoki Aihara

Yasutaka Kanayama

Kazumasa Kubotera

Naoki Fukuda

Masaki Fujioka

Yumiko Kato

Plural unit delay circuits connected in series and an output circuit that non-inverts or inverts and outputs an output signal in accordance with a set signal are included. A first unit delay circuit includes a selector that outputs a signal input to a second input terminal when the set signal is '0', and outputs a signal input to a first input terminal when the set signal is '1', and an inverter that inverts and outputs an output of the selector from a second output terminal. A second unit delay circuit includes an inverter that inverts the signal input to the first input terminal and outputs from a first output terminal, and a selector that outputs the signal input to the second input terminal when the set signal is &#x201c;0&#x201d;, and outputs an output of the inverter when the set signal is &#x201c;1&#x201d; from the second output terminal.

Variable delay circuit

A semiconductor circuit is disclosed, including a DLL circuit for supplying a desired signal-delay amount. The DLL circuit includes detecting means for detecting variations of a signal-delay amount, and delay-amount control means for generating a delay-amount control signal for controlling, depending on the variations of the signal-delay amount detected by the detecting means, the signal-delay amount of the DLL circuit. The semiconductor circuit further includes a part for monitoring circuit performance of the semiconductor circuit based on the delay-amount control signal.

Semiconductor circuit, method of monitoring semiconductor-circuit performance, method of testing semiconductor circuit, equipment for testing semiconductor circuit, and program for testing semiconductor circuit

A method for compensating for semiconductor device resistance is disclosed that includes the step of realizing a resistance equal to a desired resistance by one of combinations of multiple semiconductor devices. This step includes the step of sequentially selecting two or more of the semiconductor devices to be combined, and thereby sequentially changing a resistance realized by the selected two or more of the semiconductor devices to be combined.

Resistance compensation method, circuit having a resistance compensation function, and circuit resistance test method

An ATM exchange which is comprised of a multistage cascade connection of ATM switches of self-routing module structures which are provided with a plurality of outgoing lines and incoming lines, wherein it provides at the output side and the input side of the ATM switches output side conversion interfaces and input side conversion interfaces both for connection of adjoining ATM switches and uses optical cables to connect the output side interfaces and input side interfaces facing thereto. By this, it is possible to maintain the correct exchange operation even if the length of the transfer lines (outgoing lines and incoming lines) laid between ATM switches becomes greater along with extension of the ATM switches in the exchange.

Input and output side conversion interfaces for an ATM exchange

A television signal and ATM cell switching system for switching ATM cells of data other than television signals and for supplying one channel among a plurality of channels of television signals transmitted from a source to a subscriber to carry out one-way communication of the television signals from the source to the subscribers and two-way communication of the data other than the television signals between the network and the subscribers comprising, a television signal transmitting unit for transmitting television signals in the form of ATM cells, an ATM switching unit for switching ATM cell data other than the television signals, a television signal cell inserting circuit for receiving a plurality of channels of the television signals from the television signal transmitting unit, and for receiving ATM cell data other than the television signals after being switched by the ATM switching unit, the television signal inserting circuit comprising, a demultiplexing circuit for demultiplexing the output of the ATM switching unit to provide a plurality of outputs corresponding to respective subscribers, and a plurality of multiplexing circuits each for multiplexing the demultiplexed ATM cell received from one corresponding output of the demultiplexing circuit and one channel of the ATM cells selected in accordance with a request from the corresponding subscriber.

Television signal and ATM cell switching system

Switching system for ATM dual switch system

A virtual channel converter converts a virtual path identifier and a virtual channel identifier, e.g. in a twenty-eight (28) bit frame, attached to the header part of an incoming ATM cell on an input highway to an ATM switcher to identifiers to be attached to an outgoing ATM cell on an output highway capable of fully supporting all the combinations, two hundred fifty-six (256) for example, of a virtual path identifier and a virtual channel identifier no matter where the virtual path identifier and the virtual channel identifier are located in the twenty-eight (28) bit frame. The virtual channel converter comprises a plurality of identifier comparator units and a controller. Each of the identifier comparator units has an input identifier memory for storing an identifier attached to an ATM cell and a comparator for comparing the identifiers of an incoming ATM cell with the identifiers stored in the input identifier memory. The controller instructs respective input identifier memories to store all the values of identifiers attached to incoming ATM cells from a user to a switcher on a one-to-one basis.

Growing community of inventors

Kawasaki, Japan

Hiroshi Miyake